include/configs/socfpga_soc64_common.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
   8 #define __CONFIG_SOCFPGA_SOC64_COMMON_H__
   9
  10 #include <asm/arch/base_addr_s10.h>
  11 #include <asm/arch/handoff_s10.h>
  12 #include <linux/stringify.h>
  13
  14 /*
  15  * U-Boot general configurations
  16  */
  17 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
  18 #define CONFIG_LOADADDR                 0x2000000
  19 #define CONFIG_SYS_LOAD_ADDR            CONFIG_LOADADDR
  20 #define CONFIG_REMAKE_ELF
  21 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
  22 #define CPU_RELEASE_ADDR                0xFFD12210
  23 #define CONFIG_SYS_CACHELINE_SIZE       64
  24 #define CONFIG_SYS_MEM_RESERVE_SECURE   0       /* using OCRAM, not DDR */
  25
  26 /*
  27  * U-Boot console configurations
  28  */
  29 #define CONFIG_SYS_MAXARGS              64
  30 #define CONFIG_SYS_CBSIZE               2048
  31 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
  32                                         sizeof(CONFIG_SYS_PROMPT) + 16)
  33 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  34
  35 /* Extend size of kernel image for uncompression */
  36 #define CONFIG_SYS_BOOTM_LEN            (32 * 1024 * 1024)
  37
  38 /*
  39  * U-Boot run time memory configurations
  40  */
  41 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
  42 #define CONFIG_SYS_INIT_RAM_SIZE        0x40000
  43 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR  \
  44                                         + CONFIG_SYS_INIT_RAM_SIZE \
  45                                         - S10_HANDOFF_SIZE)
  46 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_SP_ADDR)
  47 #define CONFIG_SYS_MALLOC_LEN           (5 * 1024 * 1024)
  48
  49 /*
  50  * U-Boot environment configurations
  51  */
  52
  53 /*
  54  * QSPI support
  55  */
  56  #ifdef CONFIG_CADENCE_QSPI
  57 /* Enable it if you want to use dual-stacked mode */
  58 /*#define CONFIG_QSPI_RBF_ADDR          0x720000*/
  59
  60 /* Flash device info */
  61
  62 /*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
  63
  64 #ifndef CONFIG_SPL_BUILD
  65 #define CONFIG_MTD_PARTITIONS
  66 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
  67 #endif /* CONFIG_SPL_BUILD */
  68
  69 #ifndef __ASSEMBLY__
  70 unsigned int cm_get_qspi_controller_clk_hz(void);
  71 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
  72 #endif
  73
  74 #endif /* CONFIG_CADENCE_QSPI */
  75
  76 /*
  77  * Boot arguments passed to the boot command. The value of
  78  * CONFIG_BOOTARGS goes into the environment value "bootargs".
  79  * Do note the value will override also the chosen node in FDT blob.
  80  */
  81
  82 #ifdef CONFIG_FIT
  83 #define CONFIG_BOOTFILE "kernel.itb"
  84 #define CONFIG_BOOTCOMMAND "run fatscript; run mmcfitload;run linux_qspi_enable;" \
  85                            "run mmcfitboot"
  86 #else
  87 #define CONFIG_BOOTFILE "Image"
  88 #define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \
  89                            "run mmcboot"
  90 #endif
  91
  92 #define CONFIG_EXTRA_ENV_SETTINGS \
  93         "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  94         "bootfile=" CONFIG_BOOTFILE "\0" \
  95         "fdt_addr=8000000\0" \
  96         "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
  97         "mmcroot=/dev/mmcblk0p2\0" \
  98         "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  99                 " root=${mmcroot} rw rootwait;" \
 100                 "booti ${loadaddr} - ${fdt_addr}\0" \
 101         "mmcload=mmc rescan;" \
 102                 "load mmc 0:1 ${loadaddr} ${bootfile};" \
 103                 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
 104         "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
 105                 " root=${mmcroot} rw rootwait;" \
 106                 "bootm ${loadaddr}\0" \
 107         "mmcfitload=mmc rescan;" \
 108                 "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
 109         "linux_qspi_enable=if sf probe; then " \
 110                 "echo Enabling QSPI at Linux DTB...;" \
 111                 "fdt addr ${fdt_addr}; fdt resize;" \
 112                 "fdt set /soc/spi@ff8d2000 status okay;" \
 113                 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
 114                 " ${qspi_clock}; fi; \0" \
 115         "scriptaddr=0x02100000\0" \
 116         "scriptfile=u-boot.scr\0" \
 117         "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
 118                    "then source ${scriptaddr}; fi\0" \
 119         "socfpga_legacy_reset_compat=1\0"
 120
 121 /*
 122  * Generic Interrupt Controller Definitions
 123  */
 124 #define CONFIG_GICV2
 125
 126 /*
 127  * External memory configurations
 128  */
 129 #define PHYS_SDRAM_1                    0x0
 130 #define PHYS_SDRAM_1_SIZE               (1 * 1024 * 1024 * 1024)
 131 #define CONFIG_SYS_SDRAM_BASE           0
 132
 133 /*
 134  * Serial / UART configurations
 135  */
 136 #define CONFIG_SYS_NS16550_CLK          100000000
 137 #define CONFIG_SYS_NS16550_MEM32
 138
 139 /*
 140  * Timer & watchdog configurations
 141  */
 142 #define COUNTER_FREQUENCY               400000000
 143
 144 /*
 145  * SDMMC configurations
 146  */
 147 #ifdef CONFIG_CMD_MMC
 148 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256
 149 #endif
 150 /*
 151  * Flash configurations
 152  */
 153 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 154
 155 /* Ethernet on SoC (EMAC) */
 156 #if defined(CONFIG_CMD_NET)
 157 #define CONFIG_DW_ALTDESCRIPTOR
 158 #endif /* CONFIG_CMD_NET */
 159
 160 /*
 161  * L4 Watchdog
 162  */
 163 #ifndef CONFIG_SPL_BUILD
 164 #undef CONFIG_HW_WATCHDOG
 165 #undef CONFIG_DESIGNWARE_WATCHDOG
 166 #endif
 167 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 168 #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 169 #ifndef __ASSEMBLY__
 170 unsigned int cm_get_l4_sys_free_clk_hz(void);
 171 #define CONFIG_DW_WDT_CLOCK_KHZ         (cm_get_l4_sys_free_clk_hz() / 1000)
 172 #endif
 173 #else
 174 #define CONFIG_DW_WDT_CLOCK_KHZ         100000
 175 #endif
 176
 177 /*
 178  * SPL memory layout
 179  *
 180  * On chip RAM
 181  * 0xFFE0_0000 ...... Start of OCRAM
 182  * SPL code, rwdata
 183  * empty space
 184  * 0xFFEx_xxxx ...... Top of stack (grows down)
 185  * 0xFFEy_yyyy ...... Global Data
 186  * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
 187  * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
 188  * 0xFFE3_FFFF ...... End of OCRAM
 189  *
 190  * SDRAM
 191  * 0x0000_0000 ...... Start of SDRAM_1
 192  * unused / empty space for image loading
 193  * Size 64MB   ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
 194  * Size 1MB    ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
 195  * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
 196  *
 197  */
 198 #define CONFIG_SPL_TARGET               "spl/u-boot-spl.hex"
 199 #define CONFIG_SPL_MAX_SIZE             CONFIG_SYS_INIT_RAM_SIZE
 200 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 201 #define CONFIG_SPL_BSS_MAX_SIZE         0x100000        /* 1 MB */
 202 #define CONFIG_SPL_BSS_START_ADDR       (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
 203                                         - CONFIG_SPL_BSS_MAX_SIZE)
 204 #define CONFIG_SYS_SPL_MALLOC_SIZE      (CONFIG_SYS_MALLOC_LEN)
 205 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR \
 206                                         - CONFIG_SYS_SPL_MALLOC_SIZE)
 207
 208 /* SPL SDMMC boot support */
 209 #ifdef CONFIG_SPL_LOAD_FIT
 210 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.itb"
 211 #else
 212 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.img"
 213 #endif
 214
 215 #endif  /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */