include/configs/socfpga_soc64_common.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
   8 #define __CONFIG_SOCFPGA_SOC64_COMMON_H__
   9
  10 #include <asm/arch/base_addr_soc64.h>
  11 #include <asm/arch/handoff_soc64.h>
  12 #include <linux/stringify.h>
  13
  14 /*
  15  * U-Boot general configurations
  16  */
  17 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
  18 #define CPU_RELEASE_ADDR                0xFFD12210
  19
  20 /*
  21  * U-Boot console configurations
  22  */
  23
  24 /* Extend size of kernel image for uncompression */
  25 #define CONFIG_SYS_BOOTM_LEN            (32 * 1024 * 1024)
  26
  27 /*
  28  * U-Boot run time memory configurations
  29  */
  30 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
  31 #define CONFIG_SYS_INIT_RAM_SIZE        0x40000
  32
  33 /*
  34  * U-Boot environment configurations
  35  */
  36
  37 /*
  38  * QSPI support
  39  */
  40  #ifdef CONFIG_CADENCE_QSPI
  41 /* Enable it if you want to use dual-stacked mode */
  42 /*#define CONFIG_QSPI_RBF_ADDR          0x720000*/
  43
  44 /* Flash device info */
  45
  46 #ifndef CONFIG_SPL_BUILD
  47 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
  48 #endif /* CONFIG_SPL_BUILD */
  49
  50 #endif /* CONFIG_CADENCE_QSPI */
  51
  52 /*
  53  * Environment variable
  54  */
  55 #define CONFIG_EXTRA_ENV_SETTINGS \
  56         "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  57         "bootfile=" CONFIG_BOOTFILE "\0" \
  58         "fdt_addr=8000000\0" \
  59         "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
  60         "mmcroot=/dev/mmcblk0p2\0" \
  61         "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  62                 " root=${mmcroot} rw rootwait;" \
  63                 "booti ${loadaddr} - ${fdt_addr}\0" \
  64         "mmcload=mmc rescan;" \
  65                 "load mmc 0:1 ${loadaddr} ${bootfile};" \
  66                 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
  67         "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
  68                 " root=${mmcroot} rw rootwait;" \
  69                 "bootm ${loadaddr}\0" \
  70         "mmcfitload=mmc rescan;" \
  71                 "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
  72         "linux_qspi_enable=if sf probe; then " \
  73                 "echo Enabling QSPI at Linux DTB...;" \
  74                 "fdt addr ${fdt_addr}; fdt resize;" \
  75                 "fdt set /soc/spi@ff8d2000 status okay;" \
  76                 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
  77                 " ${qspi_clock}; fi; \0" \
  78         "scriptaddr=0x02100000\0" \
  79         "scriptfile=u-boot.scr\0" \
  80         "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
  81                    "then source ${scriptaddr}; fi\0" \
  82         "socfpga_legacy_reset_compat=1\0"
  83
  84 /*
  85  * External memory configurations
  86  */
  87 #define PHYS_SDRAM_1                    0x0
  88 #define PHYS_SDRAM_1_SIZE               (1 * 1024 * 1024 * 1024)
  89 #define CONFIG_SYS_SDRAM_BASE           0
  90
  91 /*
  92  * Serial / UART configurations
  93  */
  94 #define CONFIG_SYS_NS16550_CLK          100000000
  95 #define CONFIG_SYS_NS16550_MEM32
  96
  97 /*
  98  * SDMMC configurations
  99  */
 100 #ifdef CONFIG_CMD_MMC
 101 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256
 102 #endif
 103 /*
 104  * Flash configurations
 105  */
 106
 107 /* Ethernet on SoC (EMAC) */
 108 #if defined(CONFIG_CMD_NET)
 109 #define CONFIG_DW_ALTDESCRIPTOR
 110 #endif /* CONFIG_CMD_NET */
 111
 112 /*
 113  * L4 Watchdog
 114  */
 115 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 116 #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 117 #ifndef __ASSEMBLY__
 118 unsigned int cm_get_l4_sys_free_clk_hz(void);
 119 #define CONFIG_DW_WDT_CLOCK_KHZ         (cm_get_l4_sys_free_clk_hz() / 1000)
 120 #endif
 121 #else
 122 #define CONFIG_DW_WDT_CLOCK_KHZ         100000
 123 #endif
 124
 125 /*
 126  * SPL memory layout
 127  *
 128  * On chip RAM
 129  * 0xFFE0_0000 ...... Start of OCRAM
 130  * SPL code, rwdata
 131  * empty space
 132  * 0xFFEx_xxxx ...... Top of stack (grows down)
 133  * 0xFFEy_yyyy ...... Global Data
 134  * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
 135  * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
 136  * 0xFFE3_FFFF ...... End of OCRAM
 137  *
 138  * SDRAM
 139  * 0x0000_0000 ...... Start of SDRAM_1
 140  * unused / empty space for image loading
 141  * Size 64MB   ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
 142  * Size 1MB    ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
 143  * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
 144  *
 145  */
 146
 147 #endif  /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */