include/configs/socfpga_soc64_common.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
   8 #define __CONFIG_SOCFPGA_SOC64_COMMON_H__
   9
  10 #include <asm/arch/base_addr_soc64.h>
  11 #include <asm/arch/handoff_soc64.h>
  12 #include <linux/stringify.h>
  13
  14 /*
  15  * U-Boot general configurations
  16  */
  17 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
  18 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
  19 #define CPU_RELEASE_ADDR                0xFFD12210
  20
  21 /*
  22  * U-Boot console configurations
  23  */
  24 #define CONFIG_SYS_MAXARGS              64
  25 #define CONFIG_SYS_CBSIZE               2048
  26 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
  27                                         sizeof(CONFIG_SYS_PROMPT) + 16)
  28 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  29
  30 /* Extend size of kernel image for uncompression */
  31 #define CONFIG_SYS_BOOTM_LEN            (32 * 1024 * 1024)
  32
  33 /*
  34  * U-Boot run time memory configurations
  35  */
  36 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
  37 #define CONFIG_SYS_INIT_RAM_SIZE        0x40000
  38 #ifdef CONFIG_SPL_BUILD
  39 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR  \
  40                                         + CONFIG_SYS_INIT_RAM_SIZE \
  41                                         - SOC64_HANDOFF_SIZE)
  42 #else
  43 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_TEXT_BASE \
  44                                         + 0x100000)
  45 #endif
  46 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_SP_ADDR)
  47
  48 /*
  49  * U-Boot environment configurations
  50  */
  51
  52 /*
  53  * QSPI support
  54  */
  55  #ifdef CONFIG_CADENCE_QSPI
  56 /* Enable it if you want to use dual-stacked mode */
  57 /*#define CONFIG_QSPI_RBF_ADDR          0x720000*/
  58
  59 /* Flash device info */
  60
  61 #ifndef CONFIG_SPL_BUILD
  62 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
  63 #endif /* CONFIG_SPL_BUILD */
  64
  65 #ifndef __ASSEMBLY__
  66 unsigned int cm_get_qspi_controller_clk_hz(void);
  67 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
  68 #endif
  69
  70 #endif /* CONFIG_CADENCE_QSPI */
  71
  72 /*
  73  * Environment variable
  74  */
  75
  76 #ifdef CONFIG_FIT
  77 #define CONFIG_BOOTFILE "kernel.itb"
  78 #else
  79 #define CONFIG_BOOTFILE "Image"
  80 #endif
  81
  82 #define CONFIG_EXTRA_ENV_SETTINGS \
  83         "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  84         "bootfile=" CONFIG_BOOTFILE "\0" \
  85         "fdt_addr=8000000\0" \
  86         "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
  87         "mmcroot=/dev/mmcblk0p2\0" \
  88         "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  89                 " root=${mmcroot} rw rootwait;" \
  90                 "booti ${loadaddr} - ${fdt_addr}\0" \
  91         "mmcload=mmc rescan;" \
  92                 "load mmc 0:1 ${loadaddr} ${bootfile};" \
  93                 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
  94         "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
  95                 " root=${mmcroot} rw rootwait;" \
  96                 "bootm ${loadaddr}\0" \
  97         "mmcfitload=mmc rescan;" \
  98                 "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
  99         "linux_qspi_enable=if sf probe; then " \
 100                 "echo Enabling QSPI at Linux DTB...;" \
 101                 "fdt addr ${fdt_addr}; fdt resize;" \
 102                 "fdt set /soc/spi@ff8d2000 status okay;" \
 103                 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
 104                 " ${qspi_clock}; fi; \0" \
 105         "scriptaddr=0x02100000\0" \
 106         "scriptfile=u-boot.scr\0" \
 107         "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
 108                    "then source ${scriptaddr}; fi\0" \
 109         "socfpga_legacy_reset_compat=1\0"
 110
 111 /*
 112  * External memory configurations
 113  */
 114 #define PHYS_SDRAM_1                    0x0
 115 #define PHYS_SDRAM_1_SIZE               (1 * 1024 * 1024 * 1024)
 116 #define CONFIG_SYS_SDRAM_BASE           0
 117
 118 /*
 119  * Serial / UART configurations
 120  */
 121 #define CONFIG_SYS_NS16550_CLK          100000000
 122 #define CONFIG_SYS_NS16550_MEM32
 123
 124 /*
 125  * Timer & watchdog configurations
 126  */
 127 #define COUNTER_FREQUENCY               400000000
 128
 129 /*
 130  * SDMMC configurations
 131  */
 132 #ifdef CONFIG_CMD_MMC
 133 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256
 134 #endif
 135 /*
 136  * Flash configurations
 137  */
 138
 139 /* Ethernet on SoC (EMAC) */
 140 #if defined(CONFIG_CMD_NET)
 141 #define CONFIG_DW_ALTDESCRIPTOR
 142 #endif /* CONFIG_CMD_NET */
 143
 144 /*
 145  * L4 Watchdog
 146  */
 147 #ifndef CONFIG_SPL_BUILD
 148 #undef CONFIG_DESIGNWARE_WATCHDOG
 149 #endif
 150 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 151 #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 152 #ifndef __ASSEMBLY__
 153 unsigned int cm_get_l4_sys_free_clk_hz(void);
 154 #define CONFIG_DW_WDT_CLOCK_KHZ         (cm_get_l4_sys_free_clk_hz() / 1000)
 155 #endif
 156 #else
 157 #define CONFIG_DW_WDT_CLOCK_KHZ         100000
 158 #endif
 159
 160 /*
 161  * SPL memory layout
 162  *
 163  * On chip RAM
 164  * 0xFFE0_0000 ...... Start of OCRAM
 165  * SPL code, rwdata
 166  * empty space
 167  * 0xFFEx_xxxx ...... Top of stack (grows down)
 168  * 0xFFEy_yyyy ...... Global Data
 169  * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
 170  * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
 171  * 0xFFE3_FFFF ...... End of OCRAM
 172  *
 173  * SDRAM
 174  * 0x0000_0000 ...... Start of SDRAM_1
 175  * unused / empty space for image loading
 176  * Size 64MB   ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
 177  * Size 1MB    ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
 178  * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
 179  *
 180  */
 181 #define CONFIG_SPL_TARGET               "spl/u-boot-spl-dtb.hex"
 182 #define CONFIG_SPL_MAX_SIZE             CONFIG_SYS_INIT_RAM_SIZE
 183 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 184 #define CONFIG_SPL_BSS_MAX_SIZE         0x100000        /* 1 MB */
 185 #define CONFIG_SPL_BSS_START_ADDR       (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
 186                                         - CONFIG_SPL_BSS_MAX_SIZE)
 187 #define CONFIG_SYS_SPL_MALLOC_SIZE      (CONFIG_SYS_MALLOC_LEN)
 188 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR \
 189                                         - CONFIG_SYS_SPL_MALLOC_SIZE)
 190
 191 /* SPL SDMMC boot support */
 192 #ifdef CONFIG_SPL_LOAD_FIT
 193 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.itb"
 194 #else
 195 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.img"
 196 #endif
 197
 198 #endif  /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */