1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
7 #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
8 #define __CONFIG_SOCFPGA_SOC64_COMMON_H__
10 #include <asm/arch/base_addr_soc64.h>
11 #include <asm/arch/handoff_soc64.h>
12 #include <linux/stringify.h>
15 * U-Boot general configurations
17 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
18 #define CPU_RELEASE_ADDR 0xFFD12210
21 * U-Boot console configurations
24 /* Extend size of kernel image for uncompression */
27 * U-Boot run time memory configurations
29 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
30 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000
33 * U-Boot environment configurations
37 * Environment variable
39 #define CONFIG_EXTRA_ENV_SETTINGS \
40 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
41 "bootfile=" CONFIG_BOOTFILE "\0" \
42 "fdt_addr=8000000\0" \
43 "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
44 "mmcroot=/dev/mmcblk0p2\0" \
45 "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
46 " root=${mmcroot} rw rootwait;" \
47 "booti ${loadaddr} - ${fdt_addr}\0" \
48 "mmcload=mmc rescan;" \
49 "load mmc 0:1 ${loadaddr} ${bootfile};" \
50 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
51 "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
52 " root=${mmcroot} rw rootwait;" \
53 "bootm ${loadaddr}\0" \
54 "mmcfitload=mmc rescan;" \
55 "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
56 "linux_qspi_enable=if sf probe; then " \
57 "echo Enabling QSPI at Linux DTB...;" \
58 "fdt addr ${fdt_addr}; fdt resize;" \
59 "fdt set /soc/spi@ff8d2000 status okay;" \
60 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
61 " ${qspi_clock}; fi; \0" \
62 "scriptaddr=0x02100000\0" \
63 "scriptfile=u-boot.scr\0" \
64 "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
65 "then source ${scriptaddr}; fi\0" \
66 "socfpga_legacy_reset_compat=1\0"
69 * External memory configurations
71 #define PHYS_SDRAM_1 0x0
72 #define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024)
73 #define CONFIG_SYS_SDRAM_BASE 0
76 * Serial / UART configurations
78 #define CONFIG_SYS_NS16550_CLK 100000000
79 #define CONFIG_SYS_NS16550_MEM32
82 * SDMMC configurations
85 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
88 * Flash configurations
94 #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
96 unsigned int cm_get_l4_sys_free_clk_hz(void);
97 #define CONFIG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000)
100 #define CONFIG_DW_WDT_CLOCK_KHZ 100000
107 * 0xFFE0_0000 ...... Start of OCRAM
110 * 0xFFEx_xxxx ...... Top of stack (grows down)
111 * 0xFFEy_yyyy ...... Global Data
112 * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
113 * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
114 * 0xFFE3_FFFF ...... End of OCRAM
117 * 0x0000_0000 ...... Start of SDRAM_1
118 * unused / empty space for image loading
119 * Size 64MB ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
120 * Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
121 * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
125 #endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */