2 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef __CONFIG_TERASIC_DE0_H__
7 #define __CONFIG_TERASIC_DE0_H__
9 #include <asm/arch/base_addr_ac5.h>
12 #define CONFIG_SYS_NO_FLASH
13 #define CONFIG_DOS_PARTITION
14 #define CONFIG_FAT_WRITE
15 #define CONFIG_HW_WATCHDOG
17 #define CONFIG_CMD_ASKENV
18 #define CONFIG_CMD_BOOTZ
19 #define CONFIG_CMD_CACHE
20 #define CONFIG_CMD_DFU
21 #define CONFIG_CMD_DHCP
22 #define CONFIG_CMD_EXT4
23 #define CONFIG_CMD_EXT4_WRITE
24 #define CONFIG_CMD_FAT
25 #define CONFIG_CMD_FS_GENERIC
26 #define CONFIG_CMD_GREPENV
27 #define CONFIG_CMD_MII
28 #define CONFIG_CMD_MMC
29 #define CONFIG_CMD_PING
30 #define CONFIG_CMD_USB
31 #define CONFIG_CMD_USB_MASS_STORAGE
33 /* Memory configurations */
34 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
37 #define CONFIG_BOOTDELAY 3
38 #define CONFIG_BOOTFILE "fitImage"
39 #define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
40 #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
41 #define CONFIG_LOADADDR 0x01000000
42 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
44 /* Ethernet on SoC (EMAC) */
45 #if defined(CONFIG_CMD_NET)
46 #define CONFIG_PHY_MICREL
47 #define CONFIG_PHY_MICREL_KSZ9031
50 #define CONFIG_ENV_IS_IN_MMC
51 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
52 #define CONFIG_ENV_OFFSET 512 /* just after the MBR */
55 #define CONFIG_G_DNL_MANUFACTURER "Terasic"
57 /* Extra Environment */
58 #define CONFIG_HOSTNAME socfpga_de0_nano_soc
60 #define CONFIG_EXTRA_ENV_SETTINGS \
61 "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
62 "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
63 "bootm ${loadaddr} - ${fdt_addr}\0" \
64 "bootimage=zImage\0" \
66 "fdtimage=socfpga.dtb\0" \
67 "bootm ${loadaddr} - ${fdt_addr}\0" \
68 "mmcroot=/dev/mmcblk0p2\0" \
69 "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
70 " root=${mmcroot} rw rootwait;" \
71 "bootz ${loadaddr} - ${fdt_addr}\0" \
72 "mmcload=mmc rescan;" \
73 "load mmc 0:1 ${loadaddr} ${bootimage};" \
74 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
76 /* The rest of the configuration is shared */
77 #include <configs/socfpga_common.h>
79 #endif /* __CONFIG_TERASIC_DE0_H__ */