include/configs/socfpga_common.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   4  */
   5 #ifndef __CONFIG_SOCFPGA_COMMON_H__
   6 #define __CONFIG_SOCFPGA_COMMON_H__
   7
   8 /*
   9  * High level configuration
  10  */
  11 #define CONFIG_CLOCKS
  12
  13 #define CONFIG_SYS_BOOTMAPSZ            (64 * 1024 * 1024)
  14
  15 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  16
  17 /* add target to build it automatically upon "make" */
  18 #define CONFIG_BUILD_TARGET             "u-boot-with-spl.sfp"
  19
  20 /*
  21  * Memory configurations
  22  */
  23 #define CONFIG_NR_DRAM_BANKS            1
  24 #define PHYS_SDRAM_1                    0x0
  25 #define CONFIG_SYS_MALLOC_LEN           (64 * 1024 * 1024)
  26 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_1
  27 #define CONFIG_SYS_MEMTEST_END          PHYS_SDRAM_1_SIZE
  28 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  29 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFFF0000
  30 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
  31 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
  32 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
  33 #define CONFIG_SYS_INIT_RAM_SIZE        0x40000 /* 256KB */
  34 #endif
  35 #define CONFIG_SYS_INIT_SP_ADDR                 \
  36         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
  37
  38 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  39
  40 /*
  41  * U-Boot general configurations
  42  */
  43 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O buffer size */
  44                                                 /* Print buffer size */
  45 #define CONFIG_SYS_MAXARGS      32              /* Max number of command args */
  46 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  47                                                 /* Boot argument buffer size */
  48
  49 #ifndef CONFIG_SYS_HOSTNAME
  50 #define CONFIG_SYS_HOSTNAME     CONFIG_SYS_BOARD
  51 #endif
  52
  53 /*
  54  * Cache
  55  */
  56 #define CONFIG_SYS_L2_PL310
  57 #define CONFIG_SYS_PL310_BASE           SOCFPGA_MPUL2_ADDRESS
  58
  59 /*
  60  * EPCS/EPCQx1 Serial Flash Controller
  61  */
  62 #ifdef CONFIG_ALTERA_SPI
  63 #define CONFIG_SF_DEFAULT_SPEED         30000000
  64 /*
  65  * The base address is configurable in QSys, each board must specify the
  66  * base address based on it's particular FPGA configuration. Please note
  67  * that the address here is incremented by  0x400  from the Base address
  68  * selected in QSys, since the SPI registers are at offset +0x400.
  69  * #define CONFIG_SYS_SPI_BASE          0xff240400
  70  */
  71 #endif
  72
  73 /*
  74  * Ethernet on SoC (EMAC)
  75  */
  76 #ifdef CONFIG_CMD_NET
  77 #define CONFIG_DW_ALTDESCRIPTOR
  78 #define CONFIG_MII
  79 #endif
  80
  81 /*
  82  * FPGA Driver
  83  */
  84 #ifdef CONFIG_CMD_FPGA
  85 #define CONFIG_FPGA_COUNT               1
  86 #endif
  87
  88 /*
  89  * L4 OSC1 Timer 0
  90  */
  91 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
  92 #define CONFIG_SYS_TIMERBASE            SOCFPGA_OSC1TIMER0_ADDRESS
  93 #define CONFIG_SYS_TIMER_COUNTS_DOWN
  94 #define CONFIG_SYS_TIMER_COUNTER        (CONFIG_SYS_TIMERBASE + 0x4)
  95 #define CONFIG_SYS_TIMER_RATE           25000000
  96
  97 /*
  98  * L4 Watchdog
  99  */
 100 #ifdef CONFIG_HW_WATCHDOG
 101 #define CONFIG_DESIGNWARE_WATCHDOG
 102 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 103 #define CONFIG_DW_WDT_CLOCK_KHZ         25000
 104 #define CONFIG_WATCHDOG_TIMEOUT_MSECS   30000
 105 #endif
 106
 107 /*
 108  * MMC Driver
 109  */
 110 #ifdef CONFIG_CMD_MMC
 111 #define CONFIG_BOUNCE_BUFFER
 112 /* FIXME */
 113 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 114 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256     /* FIXME -- SPL only? */
 115 #endif
 116
 117 /*
 118  * NAND Support
 119  */
 120 #ifdef CONFIG_NAND_DENALI
 121 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 122 #define CONFIG_SYS_NAND_ONFI_DETECTION
 123 #define CONFIG_SYS_NAND_REGS_BASE       SOCFPGA_NANDREGS_ADDRESS
 124 #define CONFIG_SYS_NAND_DATA_BASE       SOCFPGA_NANDDATA_ADDRESS
 125 #endif
 126
 127 /*
 128  * I2C support
 129  */
 130 #ifndef CONFIG_DM_I2C
 131 #define CONFIG_SYS_I2C
 132 #define CONFIG_SYS_I2C_BASE             SOCFPGA_I2C0_ADDRESS
 133 #define CONFIG_SYS_I2C_BASE1            SOCFPGA_I2C1_ADDRESS
 134 #define CONFIG_SYS_I2C_BASE2            SOCFPGA_I2C2_ADDRESS
 135 #define CONFIG_SYS_I2C_BASE3            SOCFPGA_I2C3_ADDRESS
 136 /* Using standard mode which the speed up to 100Kb/s */
 137 #define CONFIG_SYS_I2C_SPEED            100000
 138 #define CONFIG_SYS_I2C_SPEED1           100000
 139 #define CONFIG_SYS_I2C_SPEED2           100000
 140 #define CONFIG_SYS_I2C_SPEED3           100000
 141 /* Address of device when used as slave */
 142 #define CONFIG_SYS_I2C_SLAVE            0x02
 143 #define CONFIG_SYS_I2C_SLAVE1           0x02
 144 #define CONFIG_SYS_I2C_SLAVE2           0x02
 145 #define CONFIG_SYS_I2C_SLAVE3           0x02
 146 #ifndef __ASSEMBLY__
 147 /* Clock supplied to I2C controller in unit of MHz */
 148 unsigned int cm_get_l4_sp_clk_hz(void);
 149 #define IC_CLK                          (cm_get_l4_sp_clk_hz() / 1000000)
 150 #endif
 151 #endif /* CONFIG_DM_I2C */
 152
 153 /*
 154  * QSPI support
 155  */
 156 /* Enable multiple SPI NOR flash manufacturers */
 157 #ifndef CONFIG_SPL_BUILD
 158 #define CONFIG_SPI_FLASH_MTD
 159 #define CONFIG_MTD_DEVICE
 160 #define CONFIG_MTD_PARTITIONS
 161 #endif
 162 /* QSPI reference clock */
 163 #ifndef __ASSEMBLY__
 164 unsigned int cm_get_qspi_controller_clk_hz(void);
 165 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
 166 #endif
 167
 168 /*
 169  * Designware SPI support
 170  */
 171
 172 /*
 173  * Serial Driver
 174  */
 175 #define CONFIG_SYS_NS16550_SERIAL
 176 #define CONFIG_SYS_NS16550_REG_SIZE     -4
 177 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 178 #define CONFIG_SYS_NS16550_COM1         SOCFPGA_UART0_ADDRESS
 179 #define CONFIG_SYS_NS16550_CLK          100000000
 180 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 181 #define CONFIG_SYS_NS16550_COM1        SOCFPGA_UART1_ADDRESS
 182 #define CONFIG_SYS_NS16550_CLK          50000000
 183 #endif
 184
 185 /*
 186  * USB
 187  */
 188
 189 /*
 190  * USB Gadget (DFU, UMS)
 191  */
 192 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
 193 #define CONFIG_SYS_DFU_DATA_BUF_SIZE    (16 * 1024 * 1024)
 194 #define DFU_DEFAULT_POLL_TIMEOUT        300
 195
 196 /* USB IDs */
 197 #define CONFIG_G_DNL_UMS_VENDOR_NUM     0x0525
 198 #define CONFIG_G_DNL_UMS_PRODUCT_NUM    0xA4A5
 199 #endif
 200
 201 /*
 202  * U-Boot environment
 203  */
 204 #if !defined(CONFIG_ENV_SIZE)
 205 #define CONFIG_ENV_SIZE                 (8 * 1024)
 206 #endif
 207
 208 /* Environment for SDMMC boot */
 209 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
 210 #define CONFIG_SYS_MMC_ENV_DEV          0 /* device 0 */
 211 #define CONFIG_ENV_OFFSET               (34 * 512) /* just after the GPT */
 212 #endif
 213
 214 /* Environment for QSPI boot */
 215 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
 216 #define CONFIG_ENV_OFFSET               0x00100000
 217 #define CONFIG_ENV_SECT_SIZE            (64 * 1024)
 218 #endif
 219
 220 /*
 221  * mtd partitioning for serial NOR flash
 222  *
 223  * device nor0 <ff705000.spi.0>, # parts = 6
 224  * #: name                size            offset          mask_flags
 225  * 0: u-boot              0x00100000      0x00000000      0
 226  * 1: env1                0x00040000      0x00100000      0
 227  * 2: env2                0x00040000      0x00140000      0
 228  * 3: UBI                 0x03e80000      0x00180000      0
 229  * 4: boot                0x00e80000      0x00180000      0
 230  * 5: rootfs              0x01000000      0x01000000      0
 231  *
 232  */
 233
 234 /*
 235  * SPL
 236  *
 237  * SRAM Memory layout:
 238  *
 239  * 0xFFFF_0000 ...... Start of SRAM
 240  * 0xFFFF_xxxx ...... Top of stack (grows down)
 241  * 0xFFFF_yyyy ...... Malloc area
 242  * 0xFFFF_zzzz ...... Global Data
 243  * 0xFFFF_FF00 ...... End of SRAM
 244  */
 245 #define CONFIG_SPL_TEXT_BASE            CONFIG_SYS_INIT_RAM_ADDR
 246 #define CONFIG_SPL_MAX_SIZE             CONFIG_SYS_INIT_RAM_SIZE
 247
 248 /* SPL SDMMC boot support */
 249 #ifdef CONFIG_SPL_MMC_SUPPORT
 250 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
 251 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot-dtb.img"
 252 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 253 #endif
 254 #else
 255 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
 256 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION      1
 257 #endif
 258 #endif
 259
 260 /* SPL QSPI boot support */
 261 #ifdef CONFIG_SPL_SPI_SUPPORT
 262 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x40000
 263 #endif
 264
 265 /* SPL NAND boot support */
 266 #ifdef CONFIG_SPL_NAND_SUPPORT
 267 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 268 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
 269 #endif
 270
 271 /*
 272  * Stack setup
 273  */
 274 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 275
 276 /* Extra Environment */
 277 #ifndef CONFIG_SPL_BUILD
 278
 279 #ifdef CONFIG_CMD_DHCP
 280 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
 281 #else
 282 #define BOOT_TARGET_DEVICES_DHCP(func)
 283 #endif
 284
 285 #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
 286 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
 287 #else
 288 #define BOOT_TARGET_DEVICES_PXE(func)
 289 #endif
 290
 291 #ifdef CONFIG_CMD_MMC
 292 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
 293 #else
 294 #define BOOT_TARGET_DEVICES_MMC(func)
 295 #endif
 296
 297 #define BOOT_TARGET_DEVICES(func) \
 298         BOOT_TARGET_DEVICES_MMC(func) \
 299         BOOT_TARGET_DEVICES_PXE(func) \
 300         BOOT_TARGET_DEVICES_DHCP(func)
 301
 302 #include <config_distro_bootcmd.h>
 303
 304 #ifndef CONFIG_EXTRA_ENV_SETTINGS
 305 #define CONFIG_EXTRA_ENV_SETTINGS \
 306         "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 307         "bootm_size=0xa000000\0" \
 308         "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
 309         "fdt_addr_r=0x02000000\0" \
 310         "scriptaddr=0x02100000\0" \
 311         "pxefile_addr_r=0x02200000\0" \
 312         "ramdisk_addr_r=0x02300000\0" \
 313         BOOTENV
 314
 315 #endif
 316 #endif
 317
 318 #endif  /* __CONFIG_SOCFPGA_COMMON_H__ */