1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
5 #ifndef __CONFIG_SOCFPGA_COMMON_H__
6 #define __CONFIG_SOCFPGA_COMMON_H__
8 /* Virtual target or real hardware */
9 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
12 * High level configuration
16 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
18 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
20 /* add target to build it automatically upon "make" */
21 #define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp"
24 * Memory configurations
26 #define CONFIG_NR_DRAM_BANKS 1
27 #define PHYS_SDRAM_1 0x0
28 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
29 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
30 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
31 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
32 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
33 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
34 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
35 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
36 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */
38 #define CONFIG_SYS_INIT_SP_OFFSET \
39 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
40 #define CONFIG_SYS_INIT_SP_ADDR \
41 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
43 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
46 * U-Boot general configurations
48 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
49 /* Print buffer size */
50 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
51 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
52 /* Boot argument buffer size */
54 #ifndef CONFIG_SYS_HOSTNAME
55 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD
61 #define CONFIG_SYS_L2_PL310
62 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
65 * EPCS/EPCQx1 Serial Flash Controller
67 #ifdef CONFIG_ALTERA_SPI
68 #define CONFIG_SF_DEFAULT_SPEED 30000000
70 * The base address is configurable in QSys, each board must specify the
71 * base address based on it's particular FPGA configuration. Please note
72 * that the address here is incremented by 0x400 from the Base address
73 * selected in QSys, since the SPI registers are at offset +0x400.
74 * #define CONFIG_SYS_SPI_BASE 0xff240400
79 * Ethernet on SoC (EMAC)
81 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
82 #define CONFIG_DW_ALTDESCRIPTOR
89 #ifdef CONFIG_CMD_FPGA
90 #define CONFIG_FPGA_COUNT 1
96 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
97 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
98 #define CONFIG_SYS_TIMER_COUNTS_DOWN
99 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
100 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
101 #define CONFIG_SYS_TIMER_RATE 2400000
103 #define CONFIG_SYS_TIMER_RATE 25000000
109 #ifdef CONFIG_HW_WATCHDOG
110 #define CONFIG_DESIGNWARE_WATCHDOG
111 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
112 #define CONFIG_DW_WDT_CLOCK_KHZ 25000
113 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000
119 #ifdef CONFIG_CMD_MMC
120 #define CONFIG_BOUNCE_BUFFER
122 /* using smaller max blk cnt to avoid flooding the limited stack we have */
123 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
129 #ifdef CONFIG_NAND_DENALI
130 #define CONFIG_SYS_MAX_NAND_DEVICE 1
131 #define CONFIG_SYS_NAND_ONFI_DETECTION
132 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
133 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
139 #ifndef CONFIG_DM_I2C
140 #define CONFIG_SYS_I2C
141 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS
142 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
143 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS
144 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS
145 /* Using standard mode which the speed up to 100Kb/s */
146 #define CONFIG_SYS_I2C_SPEED 100000
147 #define CONFIG_SYS_I2C_SPEED1 100000
148 #define CONFIG_SYS_I2C_SPEED2 100000
149 #define CONFIG_SYS_I2C_SPEED3 100000
150 /* Address of device when used as slave */
151 #define CONFIG_SYS_I2C_SLAVE 0x02
152 #define CONFIG_SYS_I2C_SLAVE1 0x02
153 #define CONFIG_SYS_I2C_SLAVE2 0x02
154 #define CONFIG_SYS_I2C_SLAVE3 0x02
156 /* Clock supplied to I2C controller in unit of MHz */
157 unsigned int cm_get_l4_sp_clk_hz(void);
158 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000)
160 #endif /* CONFIG_DM_I2C */
165 /* Enable multiple SPI NOR flash manufacturers */
166 #ifndef CONFIG_SPL_BUILD
167 #define CONFIG_SPI_FLASH_MTD
168 #define CONFIG_MTD_DEVICE
169 #define CONFIG_MTD_PARTITIONS
171 /* QSPI reference clock */
173 unsigned int cm_get_qspi_controller_clk_hz(void);
174 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
178 * Designware SPI support
184 #define CONFIG_SYS_NS16550_SERIAL
185 #define CONFIG_SYS_NS16550_REG_SIZE -4
186 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
187 #define CONFIG_SYS_NS16550_CLK 1000000
188 #elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
189 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
190 #define CONFIG_SYS_NS16550_CLK 100000000
191 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
192 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART1_ADDRESS
193 #define CONFIG_SYS_NS16550_CLK 50000000
201 * USB Gadget (DFU, UMS)
203 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
204 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024)
205 #define DFU_DEFAULT_POLL_TIMEOUT 300
208 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
209 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
215 #if !defined(CONFIG_ENV_SIZE)
216 #define CONFIG_ENV_SIZE (8 * 1024)
219 /* Environment for SDMMC boot */
220 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
221 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
222 #define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */
225 /* Environment for QSPI boot */
226 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
227 #define CONFIG_ENV_OFFSET 0x00100000
228 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
232 * mtd partitioning for serial NOR flash
234 * device nor0 <ff705000.spi.0>, # parts = 6
235 * #: name size offset mask_flags
236 * 0: u-boot 0x00100000 0x00000000 0
237 * 1: env1 0x00040000 0x00100000 0
238 * 2: env2 0x00040000 0x00140000 0
239 * 3: UBI 0x03e80000 0x00180000 0
240 * 4: boot 0x00e80000 0x00180000 0
241 * 5: rootfs 0x01000000 0x01000000 0
248 * SRAM Memory layout:
250 * 0xFFFF_0000 ...... Start of SRAM
251 * 0xFFFF_xxxx ...... Top of stack (grows down)
252 * 0xFFFF_yyyy ...... Malloc area
253 * 0xFFFF_zzzz ...... Global Data
254 * 0xFFFF_FF00 ...... End of SRAM
256 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
257 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
259 /* SPL SDMMC boot support */
260 #ifdef CONFIG_SPL_MMC_SUPPORT
261 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
262 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
263 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
266 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
267 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
271 /* SPL QSPI boot support */
272 #ifdef CONFIG_SPL_SPI_SUPPORT
273 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
276 /* SPL NAND boot support */
277 #ifdef CONFIG_SPL_NAND_SUPPORT
278 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
279 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
285 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
287 /* Extra Environment */
288 #ifndef CONFIG_SPL_BUILD
290 #ifdef CONFIG_CMD_DHCP
291 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
293 #define BOOT_TARGET_DEVICES_DHCP(func)
296 #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
297 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
299 #define BOOT_TARGET_DEVICES_PXE(func)
302 #ifdef CONFIG_CMD_MMC
303 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
305 #define BOOT_TARGET_DEVICES_MMC(func)
308 #define BOOT_TARGET_DEVICES(func) \
309 BOOT_TARGET_DEVICES_MMC(func) \
310 BOOT_TARGET_DEVICES_PXE(func) \
311 BOOT_TARGET_DEVICES_DHCP(func)
313 #include <config_distro_bootcmd.h>
315 #ifndef CONFIG_EXTRA_ENV_SETTINGS
316 #define CONFIG_EXTRA_ENV_SETTINGS \
317 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
318 "bootm_size=0xa000000\0" \
319 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
320 "fdt_addr_r=0x02000000\0" \
321 "scriptaddr=0x02100000\0" \
322 "pxefile_addr_r=0x02200000\0" \
323 "ramdisk_addr_r=0x02300000\0" \
329 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */