include/configs/socfpga_common.h

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef __CONFIG_SOCFPGA_COMMON_H__
   7 #define __CONFIG_SOCFPGA_COMMON_H__
   8
   9 /* Virtual target or real hardware */
  10 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
  11
  12 #define CONFIG_SYS_THUMB_BUILD
  13
  14 /*
  15  * High level configuration
  16  */
  17 #define CONFIG_DISPLAY_BOARDINFO_LATE
  18 #define CONFIG_SYS_NO_FLASH
  19 #define CONFIG_CLOCKS
  20
  21 #define CONFIG_CRC32_VERIFY
  22
  23 #define CONFIG_SYS_BOOTMAPSZ            (64 * 1024 * 1024)
  24
  25 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  26
  27 /* add target to build it automatically upon "make" */
  28 #define CONFIG_BUILD_TARGET             "u-boot-with-spl.sfp"
  29
  30 /*
  31  * Memory configurations
  32  */
  33 #define CONFIG_NR_DRAM_BANKS            1
  34 #define PHYS_SDRAM_1                    0x0
  35 #define CONFIG_SYS_MALLOC_LEN           (64 * 1024 * 1024)
  36 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_1
  37 #define CONFIG_SYS_MEMTEST_END          PHYS_SDRAM_1_SIZE
  38
  39 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFFF0000
  40 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
  41 #define CONFIG_SYS_INIT_SP_OFFSET               \
  42         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  43 #define CONFIG_SYS_INIT_SP_ADDR                 \
  44         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  45
  46 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  47 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  48 #define CONFIG_SYS_TEXT_BASE            0x08000040
  49 #else
  50 #define CONFIG_SYS_TEXT_BASE            0x01000040
  51 #endif
  52
  53 /*
  54  * U-Boot general configurations
  55  */
  56 #define CONFIG_SYS_LONGHELP
  57 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O buffer size */
  58 #define CONFIG_SYS_PBSIZE       \
  59         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  60                                                 /* Print buffer size */
  61 #define CONFIG_SYS_MAXARGS      32              /* Max number of command args */
  62 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  63                                                 /* Boot argument buffer size */
  64 #define CONFIG_AUTO_COMPLETE                    /* Command auto complete */
  65 #define CONFIG_CMDLINE_EDITING                  /* Command history etc */
  66
  67 #ifndef CONFIG_SYS_HOSTNAME
  68 #define CONFIG_SYS_HOSTNAME     CONFIG_SYS_BOARD
  69 #endif
  70
  71 /*
  72  * Cache
  73  */
  74 #define CONFIG_SYS_L2_PL310
  75 #define CONFIG_SYS_PL310_BASE           SOCFPGA_MPUL2_ADDRESS
  76
  77 /*
  78  * SDRAM controller
  79  */
  80 #define CONFIG_ALTERA_SDRAM
  81
  82 /*
  83  * EPCS/EPCQx1 Serial Flash Controller
  84  */
  85 #ifdef CONFIG_ALTERA_SPI
  86 #define CONFIG_SF_DEFAULT_SPEED         30000000
  87 /*
  88  * The base address is configurable in QSys, each board must specify the
  89  * base address based on it's particular FPGA configuration. Please note
  90  * that the address here is incremented by  0x400  from the Base address
  91  * selected in QSys, since the SPI registers are at offset +0x400.
  92  * #define CONFIG_SYS_SPI_BASE          0xff240400
  93  */
  94 #endif
  95
  96 /*
  97  * Ethernet on SoC (EMAC)
  98  */
  99 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 100 #define CONFIG_DW_ALTDESCRIPTOR
 101 #define CONFIG_MII
 102 #define CONFIG_AUTONEG_TIMEOUT          (15 * CONFIG_SYS_HZ)
 103 #define CONFIG_PHY_GIGE
 104 #endif
 105
 106 /*
 107  * FPGA Driver
 108  */
 109 #ifdef CONFIG_CMD_FPGA
 110 #define CONFIG_FPGA
 111 #define CONFIG_FPGA_ALTERA
 112 #define CONFIG_FPGA_SOCFPGA
 113 #define CONFIG_FPGA_COUNT               1
 114 #endif
 115
 116 /*
 117  * L4 OSC1 Timer 0
 118  */
 119 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
 120 #define CONFIG_SYS_TIMERBASE            SOCFPGA_OSC1TIMER0_ADDRESS
 121 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 122 #define CONFIG_SYS_TIMER_COUNTER        (CONFIG_SYS_TIMERBASE + 0x4)
 123 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 124 #define CONFIG_SYS_TIMER_RATE           2400000
 125 #else
 126 #define CONFIG_SYS_TIMER_RATE           25000000
 127 #endif
 128
 129 /*
 130  * L4 Watchdog
 131  */
 132 #ifdef CONFIG_HW_WATCHDOG
 133 #define CONFIG_DESIGNWARE_WATCHDOG
 134 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 135 #define CONFIG_DW_WDT_CLOCK_KHZ         25000
 136 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS   30000
 137 #endif
 138
 139 /*
 140  * MMC Driver
 141  */
 142 #ifdef CONFIG_CMD_MMC
 143 #define CONFIG_BOUNCE_BUFFER
 144 #define CONFIG_GENERIC_MMC
 145 /* FIXME */
 146 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 147 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256     /* FIXME -- SPL only? */
 148 #endif
 149
 150 /*
 151  * NAND Support
 152  */
 153 #ifdef CONFIG_NAND_DENALI
 154 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 155 #define CONFIG_SYS_NAND_MAX_CHIPS       1
 156 #define CONFIG_SYS_NAND_ONFI_DETECTION
 157 #define CONFIG_NAND_DENALI_ECC_SIZE     512
 158 #define CONFIG_SYS_NAND_REGS_BASE       SOCFPGA_NANDREGS_ADDRESS
 159 #define CONFIG_SYS_NAND_DATA_BASE       SOCFPGA_NANDDATA_ADDRESS
 160 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_DATA_BASE + 0x10)
 161 #endif
 162
 163 /*
 164  * I2C support
 165  */
 166 #define CONFIG_SYS_I2C
 167 #define CONFIG_SYS_I2C_BUS_MAX          4
 168 #define CONFIG_SYS_I2C_BASE             SOCFPGA_I2C0_ADDRESS
 169 #define CONFIG_SYS_I2C_BASE1            SOCFPGA_I2C1_ADDRESS
 170 #define CONFIG_SYS_I2C_BASE2            SOCFPGA_I2C2_ADDRESS
 171 #define CONFIG_SYS_I2C_BASE3            SOCFPGA_I2C3_ADDRESS
 172 /* Using standard mode which the speed up to 100Kb/s */
 173 #define CONFIG_SYS_I2C_SPEED            100000
 174 #define CONFIG_SYS_I2C_SPEED1           100000
 175 #define CONFIG_SYS_I2C_SPEED2           100000
 176 #define CONFIG_SYS_I2C_SPEED3           100000
 177 /* Address of device when used as slave */
 178 #define CONFIG_SYS_I2C_SLAVE            0x02
 179 #define CONFIG_SYS_I2C_SLAVE1           0x02
 180 #define CONFIG_SYS_I2C_SLAVE2           0x02
 181 #define CONFIG_SYS_I2C_SLAVE3           0x02
 182 #ifndef __ASSEMBLY__
 183 /* Clock supplied to I2C controller in unit of MHz */
 184 unsigned int cm_get_l4_sp_clk_hz(void);
 185 #define IC_CLK                          (cm_get_l4_sp_clk_hz() / 1000000)
 186 #endif
 187
 188 /*
 189  * QSPI support
 190  */
 191 /* Enable multiple SPI NOR flash manufacturers */
 192 #ifndef CONFIG_SPL_BUILD
 193 #define CONFIG_SPI_FLASH_MTD
 194 #define CONFIG_CMD_MTDPARTS
 195 #define CONFIG_MTD_DEVICE
 196 #define CONFIG_MTD_PARTITIONS
 197 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
 198 #endif
 199 /* QSPI reference clock */
 200 #ifndef __ASSEMBLY__
 201 unsigned int cm_get_qspi_controller_clk_hz(void);
 202 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
 203 #endif
 204 #define CONFIG_CQSPI_DECODER            0
 205 #define CONFIG_BOUNCE_BUFFER
 206
 207 /*
 208  * Designware SPI support
 209  */
 210
 211 /*
 212  * Serial Driver
 213  */
 214 #define CONFIG_SYS_NS16550_SERIAL
 215 #define CONFIG_SYS_NS16550_REG_SIZE     -4
 216 #define CONFIG_SYS_NS16550_COM1         SOCFPGA_UART0_ADDRESS
 217 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 218 #define CONFIG_SYS_NS16550_CLK          1000000
 219 #else
 220 #define CONFIG_SYS_NS16550_CLK          100000000
 221 #endif
 222 #define CONFIG_CONS_INDEX               1
 223 #define CONFIG_BAUDRATE                 115200
 224
 225 /*
 226  * USB
 227  */
 228 #ifdef CONFIG_CMD_USB
 229 #define CONFIG_USB_DWC2
 230 #endif
 231
 232 /*
 233  * USB Gadget (DFU, UMS)
 234  */
 235 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
 236 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 237
 238 #define CONFIG_SYS_DFU_DATA_BUF_SIZE    (32 * 1024 * 1024)
 239 #define DFU_DEFAULT_POLL_TIMEOUT        300
 240
 241 /* USB IDs */
 242 #define CONFIG_G_DNL_UMS_VENDOR_NUM     0x0525
 243 #define CONFIG_G_DNL_UMS_PRODUCT_NUM    0xA4A5
 244 #endif
 245
 246 /*
 247  * U-Boot environment
 248  */
 249 #if !defined(CONFIG_ENV_SIZE)
 250 #define CONFIG_ENV_SIZE                 4096
 251 #endif
 252
 253 /* Environment for SDMMC boot */
 254 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
 255 #define CONFIG_SYS_MMC_ENV_DEV          0       /* device 0 */
 256 #define CONFIG_ENV_OFFSET               512     /* just after the MBR */
 257 #endif
 258
 259 /* Environment for QSPI boot */
 260 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
 261 #define CONFIG_ENV_OFFSET               0x00100000
 262 #define CONFIG_ENV_SECT_SIZE            (64 * 1024)
 263 #endif
 264
 265 /*
 266  * mtd partitioning for serial NOR flash
 267  *
 268  * device nor0 <ff705000.spi.0>, # parts = 6
 269  * #: name                size            offset          mask_flags
 270  * 0: u-boot              0x00100000      0x00000000      0
 271  * 1: env1                0x00040000      0x00100000      0
 272  * 2: env2                0x00040000      0x00140000      0
 273  * 3: UBI                 0x03e80000      0x00180000      0
 274  * 4: boot                0x00e80000      0x00180000      0
 275  * 5: rootfs              0x01000000      0x01000000      0
 276  *
 277  */
 278 #if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT)
 279 #define MTDPARTS_DEFAULT        "mtdparts=ff705000.spi.0:"\
 280                                 "1m(u-boot),"           \
 281                                 "256k(env1),"           \
 282                                 "256k(env2),"           \
 283                                 "14848k(boot),"         \
 284                                 "16m(rootfs),"          \
 285                                 "-@1536k(UBI)\0"
 286 #endif
 287
 288 /* UBI and UBIFS support */
 289 #if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND)
 290 #define CONFIG_CMD_UBIFS
 291 #define CONFIG_RBTREE
 292 #define CONFIG_LZO
 293 #endif
 294
 295 /*
 296  * SPL
 297  *
 298  * SRAM Memory layout:
 299  *
 300  * 0xFFFF_0000 ...... Start of SRAM
 301  * 0xFFFF_xxxx ...... Top of stack (grows down)
 302  * 0xFFFF_yyyy ...... Malloc area
 303  * 0xFFFF_zzzz ...... Global Data
 304  * 0xFFFF_FF00 ...... End of SRAM
 305  */
 306 #define CONFIG_SPL_FRAMEWORK
 307 #define CONFIG_SPL_TEXT_BASE            CONFIG_SYS_INIT_RAM_ADDR
 308 #define CONFIG_SPL_MAX_SIZE             (64 * 1024)
 309
 310 /* SPL SDMMC boot support */
 311 #ifdef CONFIG_SPL_MMC_SUPPORT
 312 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
 313 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      2
 314 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot-dtb.img"
 315 #else
 316 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION      1
 317 #endif
 318 #endif
 319
 320 /* SPL QSPI boot support */
 321 #ifdef CONFIG_SPL_SPI_SUPPORT
 322 #define CONFIG_SPL_SPI_LOAD
 323 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x40000
 324 #endif
 325
 326 /* SPL NAND boot support */
 327 #ifdef CONFIG_SPL_NAND_SUPPORT
 328 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 329 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 330 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
 331 #endif
 332
 333 /*
 334  * Stack setup
 335  */
 336 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 337
 338 #endif  /* __CONFIG_SOCFPGA_COMMON_H__ */