include/configs/socfpga_common.h

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef __CONFIG_SOCFPGA_COMMON_H__
   7 #define __CONFIG_SOCFPGA_COMMON_H__
   8
   9
  10 /* Virtual target or real hardware */
  11 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
  12
  13 #define CONFIG_SYS_THUMB_BUILD
  14
  15 /*
  16  * High level configuration
  17  */
  18 #define CONFIG_DISPLAY_CPUINFO
  19 #define CONFIG_DISPLAY_BOARDINFO_LATE
  20 #define CONFIG_ARCH_MISC_INIT
  21 #define CONFIG_ARCH_EARLY_INIT_R
  22 #define CONFIG_SYS_NO_FLASH
  23 #define CONFIG_CLOCKS
  24
  25 #define CONFIG_CRC32_VERIFY
  26
  27 #define CONFIG_SYS_BOOTMAPSZ            (64 * 1024 * 1024)
  28
  29 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  30
  31 /* add target to build it automatically upon "make" */
  32 #define CONFIG_BUILD_TARGET             "u-boot-with-spl.sfp"
  33
  34 /*
  35  * Memory configurations
  36  */
  37 #define CONFIG_NR_DRAM_BANKS            1
  38 #define PHYS_SDRAM_1                    0x0
  39 #define CONFIG_SYS_MALLOC_LEN           (64 * 1024 * 1024)
  40 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_1
  41 #define CONFIG_SYS_MEMTEST_END          PHYS_SDRAM_1_SIZE
  42
  43 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFFF0000
  44 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
  45 #define CONFIG_SYS_INIT_SP_OFFSET               \
  46         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  47 #define CONFIG_SYS_INIT_SP_ADDR                 \
  48         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  49
  50 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  51 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  52 #define CONFIG_SYS_TEXT_BASE            0x08000040
  53 #else
  54 #define CONFIG_SYS_TEXT_BASE            0x01000040
  55 #endif
  56
  57 /*
  58  * U-Boot general configurations
  59  */
  60 #define CONFIG_SYS_LONGHELP
  61 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O buffer size */
  62 #define CONFIG_SYS_PBSIZE       \
  63         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  64                                                 /* Print buffer size */
  65 #define CONFIG_SYS_MAXARGS      32              /* Max number of command args */
  66 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  67                                                 /* Boot argument buffer size */
  68 #define CONFIG_VERSION_VARIABLE                 /* U-BOOT version */
  69 #define CONFIG_AUTO_COMPLETE                    /* Command auto complete */
  70 #define CONFIG_CMDLINE_EDITING                  /* Command history etc */
  71
  72 #ifndef CONFIG_SYS_HOSTNAME
  73 #define CONFIG_SYS_HOSTNAME     CONFIG_SYS_BOARD
  74 #endif
  75
  76 /*
  77  * Cache
  78  */
  79 #define CONFIG_SYS_CACHELINE_SIZE 32
  80 #define CONFIG_SYS_L2_PL310
  81 #define CONFIG_SYS_PL310_BASE           SOCFPGA_MPUL2_ADDRESS
  82
  83 /*
  84  * SDRAM controller
  85  */
  86 #define CONFIG_ALTERA_SDRAM
  87
  88 /*
  89  * EPCS/EPCQx1 Serial Flash Controller
  90  */
  91 #ifdef CONFIG_ALTERA_SPI
  92 #define CONFIG_SF_DEFAULT_SPEED         30000000
  93 /*
  94  * The base address is configurable in QSys, each board must specify the
  95  * base address based on it's particular FPGA configuration. Please note
  96  * that the address here is incremented by  0x400  from the Base address
  97  * selected in QSys, since the SPI registers are at offset +0x400.
  98  * #define CONFIG_SYS_SPI_BASE          0xff240400
  99  */
 100 #endif
 101
 102 /*
 103  * Ethernet on SoC (EMAC)
 104  */
 105 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 106 #define CONFIG_DW_ALTDESCRIPTOR
 107 #define CONFIG_MII
 108 #define CONFIG_AUTONEG_TIMEOUT          (15 * CONFIG_SYS_HZ)
 109 #define CONFIG_PHY_GIGE
 110 #endif
 111
 112 /*
 113  * FPGA Driver
 114  */
 115 #ifdef CONFIG_CMD_FPGA
 116 #define CONFIG_FPGA
 117 #define CONFIG_FPGA_ALTERA
 118 #define CONFIG_FPGA_SOCFPGA
 119 #define CONFIG_FPGA_COUNT               1
 120 #endif
 121
 122 /*
 123  * L4 OSC1 Timer 0
 124  */
 125 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
 126 #define CONFIG_SYS_TIMERBASE            SOCFPGA_OSC1TIMER0_ADDRESS
 127 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 128 #define CONFIG_SYS_TIMER_COUNTER        (CONFIG_SYS_TIMERBASE + 0x4)
 129 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 130 #define CONFIG_SYS_TIMER_RATE           2400000
 131 #else
 132 #define CONFIG_SYS_TIMER_RATE           25000000
 133 #endif
 134
 135 /*
 136  * L4 Watchdog
 137  */
 138 #ifdef CONFIG_HW_WATCHDOG
 139 #define CONFIG_DESIGNWARE_WATCHDOG
 140 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 141 #define CONFIG_DW_WDT_CLOCK_KHZ         25000
 142 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS   30000
 143 #endif
 144
 145 /*
 146  * MMC Driver
 147  */
 148 #ifdef CONFIG_CMD_MMC
 149 #define CONFIG_MMC
 150 #define CONFIG_BOUNCE_BUFFER
 151 #define CONFIG_GENERIC_MMC
 152 #define CONFIG_DWMMC
 153 #define CONFIG_SOCFPGA_DWMMC
 154 #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
 155 /* FIXME */
 156 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 157 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256     /* FIXME -- SPL only? */
 158 #endif
 159
 160 /*
 161  * NAND Support
 162  */
 163 #ifdef CONFIG_NAND_DENALI
 164 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 165 #define CONFIG_SYS_NAND_MAX_CHIPS       1
 166 #define CONFIG_SYS_NAND_ONFI_DETECTION
 167 #define CONFIG_NAND_DENALI_ECC_SIZE     512
 168 #define CONFIG_SYS_NAND_REGS_BASE       SOCFPGA_NANDREGS_ADDRESS
 169 #define CONFIG_SYS_NAND_DATA_BASE       SOCFPGA_NANDDATA_ADDRESS
 170 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_DATA_BASE + 0x10)
 171 #endif
 172
 173 /*
 174  * I2C support
 175  */
 176 #define CONFIG_SYS_I2C
 177 #define CONFIG_SYS_I2C_DW
 178 #define CONFIG_SYS_I2C_BUS_MAX          4
 179 #define CONFIG_SYS_I2C_BASE             SOCFPGA_I2C0_ADDRESS
 180 #define CONFIG_SYS_I2C_BASE1            SOCFPGA_I2C1_ADDRESS
 181 #define CONFIG_SYS_I2C_BASE2            SOCFPGA_I2C2_ADDRESS
 182 #define CONFIG_SYS_I2C_BASE3            SOCFPGA_I2C3_ADDRESS
 183 /* Using standard mode which the speed up to 100Kb/s */
 184 #define CONFIG_SYS_I2C_SPEED            100000
 185 #define CONFIG_SYS_I2C_SPEED1           100000
 186 #define CONFIG_SYS_I2C_SPEED2           100000
 187 #define CONFIG_SYS_I2C_SPEED3           100000
 188 /* Address of device when used as slave */
 189 #define CONFIG_SYS_I2C_SLAVE            0x02
 190 #define CONFIG_SYS_I2C_SLAVE1           0x02
 191 #define CONFIG_SYS_I2C_SLAVE2           0x02
 192 #define CONFIG_SYS_I2C_SLAVE3           0x02
 193 #ifndef __ASSEMBLY__
 194 /* Clock supplied to I2C controller in unit of MHz */
 195 unsigned int cm_get_l4_sp_clk_hz(void);
 196 #define IC_CLK                          (cm_get_l4_sp_clk_hz() / 1000000)
 197 #endif
 198
 199 /*
 200  * QSPI support
 201  */
 202 /* Enable multiple SPI NOR flash manufacturers */
 203 #ifndef CONFIG_SPL_BUILD
 204 #define CONFIG_SPI_FLASH_MTD
 205 #define CONFIG_CMD_MTDPARTS
 206 #define CONFIG_MTD_DEVICE
 207 #define CONFIG_MTD_PARTITIONS
 208 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
 209 #endif
 210 /* QSPI reference clock */
 211 #ifndef __ASSEMBLY__
 212 unsigned int cm_get_qspi_controller_clk_hz(void);
 213 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
 214 #endif
 215 #define CONFIG_CQSPI_DECODER            0
 216
 217 /*
 218  * Designware SPI support
 219  */
 220
 221 /*
 222  * Serial Driver
 223  */
 224 #define CONFIG_SYS_NS16550_SERIAL
 225 #define CONFIG_SYS_NS16550_REG_SIZE     -4
 226 #define CONFIG_SYS_NS16550_COM1         SOCFPGA_UART0_ADDRESS
 227 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 228 #define CONFIG_SYS_NS16550_CLK          1000000
 229 #else
 230 #define CONFIG_SYS_NS16550_CLK          100000000
 231 #endif
 232 #define CONFIG_CONS_INDEX               1
 233 #define CONFIG_BAUDRATE                 115200
 234
 235 /*
 236  * USB
 237  */
 238 #ifdef CONFIG_CMD_USB
 239 #define CONFIG_USB_DWC2
 240 #define CONFIG_USB_STORAGE
 241 #endif
 242
 243 /*
 244  * USB Gadget (DFU, UMS)
 245  */
 246 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
 247 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 248
 249 #define CONFIG_USB_FUNCTION_DFU
 250 #ifdef CONFIG_DM_MMC
 251 #define CONFIG_DFU_MMC
 252 #endif
 253 #define CONFIG_SYS_DFU_DATA_BUF_SIZE    (32 * 1024 * 1024)
 254 #define DFU_DEFAULT_POLL_TIMEOUT        300
 255
 256 /* USB IDs */
 257 #define CONFIG_G_DNL_UMS_VENDOR_NUM     0x0525
 258 #define CONFIG_G_DNL_UMS_PRODUCT_NUM    0xA4A5
 259 #endif
 260
 261 /*
 262  * U-Boot environment
 263  */
 264 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 265 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 266 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 267 #if !defined(CONFIG_ENV_SIZE)
 268 #define CONFIG_ENV_SIZE                 4096
 269 #endif
 270
 271 /* Environment for SDMMC boot */
 272 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
 273 #define CONFIG_SYS_MMC_ENV_DEV          0       /* device 0 */
 274 #define CONFIG_ENV_OFFSET               512     /* just after the MBR */
 275 #endif
 276
 277 /* Environment for QSPI boot */
 278 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
 279 #define CONFIG_ENV_OFFSET               0x00100000
 280 #define CONFIG_ENV_SECT_SIZE            (64 * 1024)
 281 #endif
 282
 283 /*
 284  * mtd partitioning for serial NOR flash
 285  *
 286  * device nor0 <ff705000.spi.0>, # parts = 6
 287  * #: name                size            offset          mask_flags
 288  * 0: u-boot              0x00100000      0x00000000      0
 289  * 1: env1                0x00040000      0x00100000      0
 290  * 2: env2                0x00040000      0x00140000      0
 291  * 3: UBI                 0x03e80000      0x00180000      0
 292  * 4: boot                0x00e80000      0x00180000      0
 293  * 5: rootfs              0x01000000      0x01000000      0
 294  *
 295  */
 296 #if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT)
 297 #define MTDPARTS_DEFAULT        "mtdparts=ff705000.spi.0:"\
 298                                 "1m(u-boot),"           \
 299                                 "256k(env1),"           \
 300                                 "256k(env2),"           \
 301                                 "14848k(boot),"         \
 302                                 "16m(rootfs),"          \
 303                                 "-@1536k(UBI)\0"
 304 #endif
 305
 306 /* UBI and UBIFS support */
 307 #if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND)
 308 #define CONFIG_CMD_UBI
 309 #define CONFIG_CMD_UBIFS
 310 #define CONFIG_RBTREE
 311 #define CONFIG_LZO
 312 #endif
 313
 314 /*
 315  * SPL
 316  *
 317  * SRAM Memory layout:
 318  *
 319  * 0xFFFF_0000 ...... Start of SRAM
 320  * 0xFFFF_xxxx ...... Top of stack (grows down)
 321  * 0xFFFF_yyyy ...... Malloc area
 322  * 0xFFFF_zzzz ...... Global Data
 323  * 0xFFFF_FF00 ...... End of SRAM
 324  */
 325 #define CONFIG_SPL_FRAMEWORK
 326 #define CONFIG_SPL_RAM_DEVICE
 327 #define CONFIG_SPL_TEXT_BASE            CONFIG_SYS_INIT_RAM_ADDR
 328 #define CONFIG_SPL_MAX_SIZE             (64 * 1024)
 329 #ifdef CONFIG_SPL_BUILD
 330 #define CONFIG_SYS_MALLOC_SIMPLE
 331 #endif
 332
 333 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 334 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 335 #define CONFIG_SPL_WATCHDOG_SUPPORT
 336 #define CONFIG_SPL_SERIAL_SUPPORT
 337 #ifdef CONFIG_DM_MMC
 338 #define CONFIG_SPL_MMC_SUPPORT
 339 #endif
 340 #ifdef CONFIG_DM_SPI
 341 #define CONFIG_SPL_SPI_SUPPORT
 342 #endif
 343 #ifdef CONFIG_SPL_NAND_DENALI
 344 #define CONFIG_SPL_NAND_SUPPORT
 345 #endif
 346
 347 /* SPL SDMMC boot support */
 348 #ifdef CONFIG_SPL_MMC_SUPPORT
 349 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
 350 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      2
 351 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot-dtb.img"
 352 #define CONFIG_SPL_LIBDISK_SUPPORT
 353 #else
 354 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      3
 355 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */
 356 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS      800 /* 400 KB */
 357 #endif
 358 #endif
 359
 360 /* SPL QSPI boot support */
 361 #ifdef CONFIG_SPL_SPI_SUPPORT
 362 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 363 #define CONFIG_SPL_SPI_LOAD
 364 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x40000
 365 #endif
 366
 367 /* SPL NAND boot support */
 368 #ifdef CONFIG_SPL_NAND_SUPPORT
 369 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 370 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 371 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
 372 #endif
 373
 374 /*
 375  * Stack setup
 376  */
 377 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 378
 379 #endif  /* __CONFIG_SOCFPGA_COMMON_H__ */