include/configs/socfpga_common.h

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef __CONFIG_SOCFPGA_COMMON_H__
   7 #define __CONFIG_SOCFPGA_COMMON_H__
   8
   9
  10 /* Virtual target or real hardware */
  11 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
  12
  13 #define CONFIG_SYS_THUMB_BUILD
  14
  15 /*
  16  * High level configuration
  17  */
  18 #define CONFIG_DISPLAY_CPUINFO
  19 #define CONFIG_DISPLAY_BOARDINFO_LATE
  20 #define CONFIG_ARCH_MISC_INIT
  21 #define CONFIG_ARCH_EARLY_INIT_R
  22 #define CONFIG_SYS_NO_FLASH
  23 #define CONFIG_CLOCKS
  24
  25 #define CONFIG_CRC32_VERIFY
  26
  27 #define CONFIG_FIT
  28 #define CONFIG_SYS_BOOTMAPSZ            (64 * 1024 * 1024)
  29
  30 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  31
  32 /* add target to build it automatically upon "make" */
  33 #define CONFIG_BUILD_TARGET             "u-boot-with-spl.sfp"
  34
  35 /*
  36  * Memory configurations
  37  */
  38 #define CONFIG_NR_DRAM_BANKS            1
  39 #define PHYS_SDRAM_1                    0x0
  40 #define CONFIG_SYS_MALLOC_LEN           (64 * 1024 * 1024)
  41 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_1
  42 #define CONFIG_SYS_MEMTEST_END          PHYS_SDRAM_1_SIZE
  43
  44 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFFF0000
  45 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
  46 #define CONFIG_SYS_INIT_SP_OFFSET               \
  47         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  48 #define CONFIG_SYS_INIT_SP_ADDR                 \
  49         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  50
  51 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  52 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  53 #define CONFIG_SYS_TEXT_BASE            0x08000040
  54 #else
  55 #define CONFIG_SYS_TEXT_BASE            0x01000040
  56 #endif
  57
  58 /*
  59  * U-Boot general configurations
  60  */
  61 #define CONFIG_SYS_LONGHELP
  62 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O buffer size */
  63 #define CONFIG_SYS_PBSIZE       \
  64         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  65                                                 /* Print buffer size */
  66 #define CONFIG_SYS_MAXARGS      32              /* Max number of command args */
  67 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  68                                                 /* Boot argument buffer size */
  69 #define CONFIG_VERSION_VARIABLE                 /* U-BOOT version */
  70 #define CONFIG_AUTO_COMPLETE                    /* Command auto complete */
  71 #define CONFIG_CMDLINE_EDITING                  /* Command history etc */
  72 #define CONFIG_SYS_HUSH_PARSER
  73
  74 #ifndef CONFIG_SYS_HOSTNAME
  75 #define CONFIG_SYS_HOSTNAME     CONFIG_SYS_BOARD
  76 #endif
  77
  78 /*
  79  * Cache
  80  */
  81 #define CONFIG_SYS_CACHELINE_SIZE 32
  82 #define CONFIG_SYS_L2_PL310
  83 #define CONFIG_SYS_PL310_BASE           SOCFPGA_MPUL2_ADDRESS
  84
  85 /*
  86  * SDRAM controller
  87  */
  88 #define CONFIG_ALTERA_SDRAM
  89
  90 /*
  91  * EPCS/EPCQx1 Serial Flash Controller
  92  */
  93 #ifdef CONFIG_ALTERA_SPI
  94 #define CONFIG_CMD_SPI
  95 #define CONFIG_CMD_SF
  96 #define CONFIG_SF_DEFAULT_SPEED         30000000
  97 #define CONFIG_SPI_FLASH_BAR
  98 /*
  99  * The base address is configurable in QSys, each board must specify the
 100  * base address based on it's particular FPGA configuration. Please note
 101  * that the address here is incremented by  0x400  from the Base address
 102  * selected in QSys, since the SPI registers are at offset +0x400.
 103  * #define CONFIG_SYS_SPI_BASE          0xff240400
 104  */
 105 #endif
 106
 107 /*
 108  * Ethernet on SoC (EMAC)
 109  */
 110 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 111 #define CONFIG_DW_ALTDESCRIPTOR
 112 #define CONFIG_MII
 113 #define CONFIG_AUTONEG_TIMEOUT          (15 * CONFIG_SYS_HZ)
 114 #define CONFIG_PHY_GIGE
 115 #endif
 116
 117 /*
 118  * FPGA Driver
 119  */
 120 #ifdef CONFIG_CMD_FPGA
 121 #define CONFIG_FPGA
 122 #define CONFIG_FPGA_ALTERA
 123 #define CONFIG_FPGA_SOCFPGA
 124 #define CONFIG_FPGA_COUNT               1
 125 #endif
 126
 127 /*
 128  * L4 OSC1 Timer 0
 129  */
 130 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
 131 #define CONFIG_SYS_TIMERBASE            SOCFPGA_OSC1TIMER0_ADDRESS
 132 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 133 #define CONFIG_SYS_TIMER_COUNTER        (CONFIG_SYS_TIMERBASE + 0x4)
 134 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 135 #define CONFIG_SYS_TIMER_RATE           2400000
 136 #else
 137 #define CONFIG_SYS_TIMER_RATE           25000000
 138 #endif
 139
 140 /*
 141  * L4 Watchdog
 142  */
 143 #ifdef CONFIG_HW_WATCHDOG
 144 #define CONFIG_DESIGNWARE_WATCHDOG
 145 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 146 #define CONFIG_DW_WDT_CLOCK_KHZ         25000
 147 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS   30000
 148 #endif
 149
 150 /*
 151  * MMC Driver
 152  */
 153 #ifdef CONFIG_CMD_MMC
 154 #define CONFIG_MMC
 155 #define CONFIG_BOUNCE_BUFFER
 156 #define CONFIG_GENERIC_MMC
 157 #define CONFIG_DWMMC
 158 #define CONFIG_SOCFPGA_DWMMC
 159 #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
 160 /* FIXME */
 161 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 162 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256     /* FIXME -- SPL only? */
 163 #endif
 164
 165 /*
 166  * NAND Support
 167  */
 168 #ifdef CONFIG_NAND_DENALI
 169 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 170 #define CONFIG_SYS_NAND_MAX_CHIPS       1
 171 #define CONFIG_SYS_NAND_ONFI_DETECTION
 172 #define CONFIG_NAND_DENALI_ECC_SIZE     512
 173 #define CONFIG_SYS_NAND_REGS_BASE       SOCFPGA_NANDREGS_ADDRESS
 174 #define CONFIG_SYS_NAND_DATA_BASE       SOCFPGA_NANDDATA_ADDRESS
 175 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_DATA_BASE + 0x10)
 176 #endif
 177
 178 /*
 179  * I2C support
 180  */
 181 #define CONFIG_SYS_I2C
 182 #define CONFIG_SYS_I2C_DW
 183 #define CONFIG_SYS_I2C_BUS_MAX          4
 184 #define CONFIG_SYS_I2C_BASE             SOCFPGA_I2C0_ADDRESS
 185 #define CONFIG_SYS_I2C_BASE1            SOCFPGA_I2C1_ADDRESS
 186 #define CONFIG_SYS_I2C_BASE2            SOCFPGA_I2C2_ADDRESS
 187 #define CONFIG_SYS_I2C_BASE3            SOCFPGA_I2C3_ADDRESS
 188 /* Using standard mode which the speed up to 100Kb/s */
 189 #define CONFIG_SYS_I2C_SPEED            100000
 190 #define CONFIG_SYS_I2C_SPEED1           100000
 191 #define CONFIG_SYS_I2C_SPEED2           100000
 192 #define CONFIG_SYS_I2C_SPEED3           100000
 193 /* Address of device when used as slave */
 194 #define CONFIG_SYS_I2C_SLAVE            0x02
 195 #define CONFIG_SYS_I2C_SLAVE1           0x02
 196 #define CONFIG_SYS_I2C_SLAVE2           0x02
 197 #define CONFIG_SYS_I2C_SLAVE3           0x02
 198 #ifndef __ASSEMBLY__
 199 /* Clock supplied to I2C controller in unit of MHz */
 200 unsigned int cm_get_l4_sp_clk_hz(void);
 201 #define IC_CLK                          (cm_get_l4_sp_clk_hz() / 1000000)
 202 #endif
 203 #define CONFIG_CMD_I2C
 204
 205 /*
 206  * QSPI support
 207  */
 208 /* Enable multiple SPI NOR flash manufacturers */
 209 #ifndef CONFIG_SPL_BUILD
 210 #define CONFIG_SPI_FLASH_MTD
 211 #define CONFIG_CMD_MTDPARTS
 212 #define CONFIG_MTD_DEVICE
 213 #define CONFIG_MTD_PARTITIONS
 214 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
 215 #endif
 216 /* QSPI reference clock */
 217 #ifndef __ASSEMBLY__
 218 unsigned int cm_get_qspi_controller_clk_hz(void);
 219 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
 220 #endif
 221 #define CONFIG_CQSPI_DECODER            0
 222 #define CONFIG_CMD_SF
 223 #define CONFIG_SPI_FLASH_BAR
 224
 225 /*
 226  * Designware SPI support
 227  */
 228 #define CONFIG_CMD_SPI
 229
 230 /*
 231  * Serial Driver
 232  */
 233 #define CONFIG_SYS_NS16550_SERIAL
 234 #define CONFIG_SYS_NS16550_REG_SIZE     -4
 235 #define CONFIG_SYS_NS16550_COM1         SOCFPGA_UART0_ADDRESS
 236 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 237 #define CONFIG_SYS_NS16550_CLK          1000000
 238 #else
 239 #define CONFIG_SYS_NS16550_CLK          100000000
 240 #endif
 241 #define CONFIG_CONS_INDEX               1
 242 #define CONFIG_BAUDRATE                 115200
 243
 244 /*
 245  * USB
 246  */
 247 #ifdef CONFIG_CMD_USB
 248 #define CONFIG_USB_DWC2
 249 #define CONFIG_USB_STORAGE
 250 #endif
 251
 252 /*
 253  * USB Gadget (DFU, UMS)
 254  */
 255 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
 256 #define CONFIG_USB_GADGET
 257 #define CONFIG_USB_GADGET_DWC2_OTG
 258 #define CONFIG_USB_GADGET_DUALSPEED
 259 #define CONFIG_USB_GADGET_VBUS_DRAW     2
 260
 261 /* USB Composite download gadget - g_dnl */
 262 #define CONFIG_USB_GADGET_DOWNLOAD
 263 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 264
 265 #define CONFIG_USB_FUNCTION_DFU
 266 #ifdef CONFIG_DM_MMC
 267 #define CONFIG_DFU_MMC
 268 #endif
 269 #define CONFIG_SYS_DFU_DATA_BUF_SIZE    (32 * 1024 * 1024)
 270 #define DFU_DEFAULT_POLL_TIMEOUT        300
 271
 272 /* USB IDs */
 273 #define CONFIG_G_DNL_VENDOR_NUM         0x0525  /* NetChip */
 274 #define CONFIG_G_DNL_PRODUCT_NUM        0xA4A5  /* Linux-USB File-backed Storage Gadget */
 275 #define CONFIG_G_DNL_UMS_VENDOR_NUM     CONFIG_G_DNL_VENDOR_NUM
 276 #define CONFIG_G_DNL_UMS_PRODUCT_NUM    CONFIG_G_DNL_PRODUCT_NUM
 277 #ifndef CONFIG_G_DNL_MANUFACTURER
 278 #define CONFIG_G_DNL_MANUFACTURER       CONFIG_SYS_VENDOR
 279 #endif
 280 #endif
 281
 282 /*
 283  * U-Boot environment
 284  */
 285 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 286 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 287 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 288 #define CONFIG_ENV_SIZE                 4096
 289
 290 /* Environment for SDMMC boot */
 291 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
 292 #define CONFIG_SYS_MMC_ENV_DEV          0       /* device 0 */
 293 #define CONFIG_ENV_OFFSET               512     /* just after the MBR */
 294 #endif
 295
 296 /*
 297  * mtd partitioning for serial NOR flash
 298  *
 299  * device nor0 <ff705000.spi.0>, # parts = 6
 300  * #: name                size            offset          mask_flags
 301  * 0: u-boot              0x00100000      0x00000000      0
 302  * 1: env1                0x00040000      0x00100000      0
 303  * 2: env2                0x00040000      0x00140000      0
 304  * 3: UBI                 0x03e80000      0x00180000      0
 305  * 4: boot                0x00e80000      0x00180000      0
 306  * 5: rootfs              0x01000000      0x01000000      0
 307  *
 308  */
 309 #if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT)
 310 #define MTDPARTS_DEFAULT        "mtdparts=ff705000.spi.0:"\
 311                                 "1m(u-boot),"           \
 312                                 "256k(env1),"           \
 313                                 "256k(env2),"           \
 314                                 "14848k(boot),"         \
 315                                 "16m(rootfs),"          \
 316                                 "-@1536k(UBI)\0"
 317 #endif
 318
 319 /* UBI and UBIFS support */
 320 #if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND)
 321 #define CONFIG_CMD_UBI
 322 #define CONFIG_CMD_UBIFS
 323 #define CONFIG_RBTREE
 324 #define CONFIG_LZO
 325 #endif
 326
 327 /*
 328  * SPL
 329  *
 330  * SRAM Memory layout:
 331  *
 332  * 0xFFFF_0000 ...... Start of SRAM
 333  * 0xFFFF_xxxx ...... Top of stack (grows down)
 334  * 0xFFFF_yyyy ...... Malloc area
 335  * 0xFFFF_zzzz ...... Global Data
 336  * 0xFFFF_FF00 ...... End of SRAM
 337  */
 338 #define CONFIG_SPL_FRAMEWORK
 339 #define CONFIG_SPL_RAM_DEVICE
 340 #define CONFIG_SPL_TEXT_BASE            CONFIG_SYS_INIT_RAM_ADDR
 341 #define CONFIG_SPL_MAX_SIZE             (64 * 1024)
 342 #ifdef CONFIG_SPL_BUILD
 343 #define CONFIG_SYS_MALLOC_SIMPLE
 344 #endif
 345
 346 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 347 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 348 #define CONFIG_SPL_WATCHDOG_SUPPORT
 349 #define CONFIG_SPL_SERIAL_SUPPORT
 350 #ifdef CONFIG_DM_MMC
 351 #define CONFIG_SPL_MMC_SUPPORT
 352 #endif
 353 #ifdef CONFIG_DM_SPI
 354 #define CONFIG_SPL_SPI_SUPPORT
 355 #endif
 356 #ifdef CONFIG_SPL_NAND_DENALI
 357 #define CONFIG_SPL_NAND_SUPPORT
 358 #endif
 359
 360 /* SPL SDMMC boot support */
 361 #ifdef CONFIG_SPL_MMC_SUPPORT
 362 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
 363 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      2
 364 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot-dtb.img"
 365 #define CONFIG_SPL_LIBDISK_SUPPORT
 366 #else
 367 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      3
 368 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */
 369 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS      800 /* 400 KB */
 370 #endif
 371 #endif
 372
 373 /* SPL QSPI boot support */
 374 #ifdef CONFIG_SPL_SPI_SUPPORT
 375 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 376 #define CONFIG_SPL_SPI_LOAD
 377 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x40000
 378 #endif
 379
 380 /* SPL NAND boot support */
 381 #ifdef CONFIG_SPL_NAND_SUPPORT
 382 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 383 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 384 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
 385 #endif
 386
 387 /*
 388  * Stack setup
 389  */
 390 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 391
 392 #endif  /* __CONFIG_SOCFPGA_COMMON_H__ */