1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
5 #ifndef __CONFIG_SOCFPGA_COMMON_H__
6 #define __CONFIG_SOCFPGA_COMMON_H__
8 #include <linux/stringify.h>
11 * Memory configurations
13 #define PHYS_SDRAM_1 0x0
14 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
15 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
16 #define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
17 #define CONFIG_SPL_PAD_TO 0x10000
18 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
19 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
20 #define CONFIG_SPL_PAD_TO 0x40000
21 /* SPL memory allocation configuration, this is for FAT implementation */
22 #ifndef CONFIG_SYS_SPL_MALLOC_SIZE
23 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000
25 #define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
26 CONFIG_SYS_SPL_MALLOC_SIZE)
27 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \
28 CONFIG_SYS_INIT_RAM_SIZE)
32 * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
33 * SRAM as bootcounter storage. Make sure to not put the stack directly
34 * at this address to not overwrite the bootcounter by checking, if the
35 * bootcounter address is located in the internal SRAM.
37 #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
38 (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
39 CONFIG_SYS_INIT_RAM_SIZE)))
40 #define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR
42 #define CONFIG_SPL_STACK \
43 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
47 * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
48 * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
49 * in U-Boot pre-reloc is higher than in SPL.
51 #if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
52 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR
54 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
57 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
60 * U-Boot general configurations
62 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
63 /* Print buffer size */
64 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
65 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
66 /* Boot argument buffer size */
71 #define CONFIG_SYS_L2_PL310
72 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
75 * Ethernet on SoC (EMAC)
78 #define CONFIG_DW_ALTDESCRIPTOR
84 #ifdef CONFIG_CMD_FPGA
85 #define CONFIG_FPGA_COUNT 1
92 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
93 #define CONFIG_SYS_TIMER_COUNTS_DOWN
94 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
95 #ifndef CONFIG_SYS_TIMER_RATE
96 #define CONFIG_SYS_TIMER_RATE 25000000
103 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
104 #define CONFIG_DW_WDT_CLOCK_KHZ 25000
109 #ifdef CONFIG_CMD_MMC
111 /* using smaller max blk cnt to avoid flooding the limited stack we have */
112 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
118 #ifdef CONFIG_NAND_DENALI
119 #define CONFIG_SYS_MAX_NAND_DEVICE 1
120 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
121 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
127 /* QSPI reference clock */
129 unsigned int cm_get_qspi_controller_clk_hz(void);
130 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
138 * USB Gadget (DFU, UMS)
140 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
141 #define DFU_DEFAULT_POLL_TIMEOUT 300
144 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
145 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
152 /* Environment for SDMMC boot */
154 /* Environment for QSPI boot */
159 * SRAM Memory layout for gen 5:
161 * 0xFFFF_0000 ...... Start of SRAM
162 * 0xFFFF_xxxx ...... Top of stack (grows down)
163 * 0xFFFF_yyyy ...... Global Data
164 * 0xFFFF_zzzz ...... Malloc area
165 * 0xFFFF_FFFF ...... End of SRAM
167 * SRAM Memory layout for Arria 10:
168 * 0xFFE0_0000 ...... Start of SRAM (bottom)
169 * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
170 * 0xFFEy_yyyy ...... Global Data
171 * 0xFFEz_zzzz ...... Malloc area (grows up to top)
172 * 0xFFE3_FFFF ...... End of SRAM (top)
174 #ifndef CONFIG_SPL_TEXT_BASE
175 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
178 /* SPL SDMMC boot support */
179 #ifdef CONFIG_SPL_MMC
180 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
181 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
185 /* SPL QSPI boot support */
187 /* SPL NAND boot support */
189 /* Extra Environment */
190 #ifndef CONFIG_SPL_BUILD
192 #ifdef CONFIG_CMD_DHCP
193 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
195 #define BOOT_TARGET_DEVICES_DHCP(func)
198 #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
199 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
201 #define BOOT_TARGET_DEVICES_PXE(func)
204 #ifdef CONFIG_CMD_MMC
205 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
207 #define BOOT_TARGET_DEVICES_MMC(func)
210 #define BOOT_TARGET_DEVICES(func) \
211 BOOT_TARGET_DEVICES_MMC(func) \
212 BOOT_TARGET_DEVICES_PXE(func) \
213 BOOT_TARGET_DEVICES_DHCP(func)
215 #include <config_distro_bootcmd.h>
217 #ifndef CONFIG_EXTRA_ENV_SETTINGS
218 #define CONFIG_EXTRA_ENV_SETTINGS \
219 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
220 "bootm_size=0xa000000\0" \
221 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
222 "fdt_addr_r=0x02000000\0" \
223 "scriptaddr=0x02100000\0" \
224 "pxefile_addr_r=0x02200000\0" \
225 "ramdisk_addr_r=0x02300000\0" \
226 "socfpga_legacy_reset_compat=1\0" \
232 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */