include/configs/socfpga_common.h

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef __CONFIG_SOCFPGA_COMMON_H__
   7 #define __CONFIG_SOCFPGA_COMMON_H__
   8
   9
  10 /* Virtual target or real hardware */
  11 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
  12
  13 #define CONFIG_SYS_THUMB_BUILD
  14
  15 /*
  16  * High level configuration
  17  */
  18 #define CONFIG_DISPLAY_CPUINFO
  19 #define CONFIG_DISPLAY_BOARDINFO_LATE
  20 #define CONFIG_ARCH_MISC_INIT
  21 #define CONFIG_ARCH_EARLY_INIT_R
  22 #define CONFIG_SYS_NO_FLASH
  23 #define CONFIG_CLOCKS
  24
  25 #define CONFIG_CRC32_VERIFY
  26
  27 #define CONFIG_FIT
  28 #define CONFIG_OF_LIBFDT
  29 #define CONFIG_SYS_BOOTMAPSZ            (64 * 1024 * 1024)
  30
  31 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  32
  33 /*
  34  * Memory configurations
  35  */
  36 #define CONFIG_NR_DRAM_BANKS            1
  37 #define PHYS_SDRAM_1                    0x0
  38 #define CONFIG_SYS_MALLOC_LEN           (64 * 1024 * 1024)
  39 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_1
  40 #define CONFIG_SYS_MEMTEST_END          PHYS_SDRAM_1_SIZE
  41
  42 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFFF0000
  43 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
  44 #define CONFIG_SYS_INIT_SP_OFFSET               \
  45         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  46 #define CONFIG_SYS_INIT_SP_ADDR                 \
  47         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  48
  49 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  50 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  51 #define CONFIG_SYS_TEXT_BASE            0x08000040
  52 #else
  53 #define CONFIG_SYS_TEXT_BASE            0x01000040
  54 #endif
  55
  56 /*
  57  * U-Boot general configurations
  58  */
  59 #define CONFIG_SYS_LONGHELP
  60 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O buffer size */
  61 #define CONFIG_SYS_PBSIZE       \
  62         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  63                                                 /* Print buffer size */
  64 #define CONFIG_SYS_MAXARGS      32              /* Max number of command args */
  65 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  66                                                 /* Boot argument buffer size */
  67 #define CONFIG_VERSION_VARIABLE                 /* U-BOOT version */
  68 #define CONFIG_AUTO_COMPLETE                    /* Command auto complete */
  69 #define CONFIG_CMDLINE_EDITING                  /* Command history etc */
  70 #define CONFIG_SYS_HUSH_PARSER
  71
  72 #ifndef CONFIG_SYS_HOSTNAME
  73 #define CONFIG_SYS_HOSTNAME     CONFIG_SYS_BOARD
  74 #endif
  75
  76 /*
  77  * Cache
  78  */
  79 #define CONFIG_SYS_CACHELINE_SIZE 32
  80 #define CONFIG_SYS_L2_PL310
  81 #define CONFIG_SYS_PL310_BASE           SOCFPGA_MPUL2_ADDRESS
  82
  83 /*
  84  * SDRAM controller
  85  */
  86 #define CONFIG_ALTERA_SDRAM
  87
  88 /*
  89  * EPCS/EPCQx1 Serial Flash Controller
  90  */
  91 #ifdef CONFIG_ALTERA_SPI
  92 #define CONFIG_CMD_SPI
  93 #define CONFIG_CMD_SF
  94 #define CONFIG_SF_DEFAULT_SPEED         30000000
  95 #define CONFIG_SPI_FLASH_BAR
  96 /*
  97  * The base address is configurable in QSys, each board must specify the
  98  * base address based on it's particular FPGA configuration. Please note
  99  * that the address here is incremented by  0x400  from the Base address
 100  * selected in QSys, since the SPI registers are at offset +0x400.
 101  * #define CONFIG_SYS_SPI_BASE          0xff240400
 102  */
 103 #endif
 104
 105 /*
 106  * Ethernet on SoC (EMAC)
 107  */
 108 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 109 #define CONFIG_DW_ALTDESCRIPTOR
 110 #define CONFIG_MII
 111 #define CONFIG_AUTONEG_TIMEOUT          (15 * CONFIG_SYS_HZ)
 112 #define CONFIG_PHY_GIGE
 113 #endif
 114
 115 /*
 116  * FPGA Driver
 117  */
 118 #ifdef CONFIG_CMD_FPGA
 119 #define CONFIG_FPGA
 120 #define CONFIG_FPGA_ALTERA
 121 #define CONFIG_FPGA_SOCFPGA
 122 #define CONFIG_FPGA_COUNT               1
 123 #endif
 124
 125 /*
 126  * L4 OSC1 Timer 0
 127  */
 128 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
 129 #define CONFIG_SYS_TIMERBASE            SOCFPGA_OSC1TIMER0_ADDRESS
 130 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 131 #define CONFIG_SYS_TIMER_COUNTER        (CONFIG_SYS_TIMERBASE + 0x4)
 132 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 133 #define CONFIG_SYS_TIMER_RATE           2400000
 134 #else
 135 #define CONFIG_SYS_TIMER_RATE           25000000
 136 #endif
 137
 138 /*
 139  * L4 Watchdog
 140  */
 141 #ifdef CONFIG_HW_WATCHDOG
 142 #define CONFIG_DESIGNWARE_WATCHDOG
 143 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 144 #define CONFIG_DW_WDT_CLOCK_KHZ         25000
 145 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS   30000
 146 #endif
 147
 148 /*
 149  * MMC Driver
 150  */
 151 #ifdef CONFIG_CMD_MMC
 152 #define CONFIG_MMC
 153 #define CONFIG_BOUNCE_BUFFER
 154 #define CONFIG_GENERIC_MMC
 155 #define CONFIG_DWMMC
 156 #define CONFIG_SOCFPGA_DWMMC
 157 #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
 158 /* FIXME */
 159 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 160 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256     /* FIXME -- SPL only? */
 161 #endif
 162
 163 /*
 164  * I2C support
 165  */
 166 #define CONFIG_SYS_I2C
 167 #define CONFIG_SYS_I2C_DW
 168 #define CONFIG_SYS_I2C_BUS_MAX          4
 169 #define CONFIG_SYS_I2C_BASE             SOCFPGA_I2C0_ADDRESS
 170 #define CONFIG_SYS_I2C_BASE1            SOCFPGA_I2C1_ADDRESS
 171 #define CONFIG_SYS_I2C_BASE2            SOCFPGA_I2C2_ADDRESS
 172 #define CONFIG_SYS_I2C_BASE3            SOCFPGA_I2C3_ADDRESS
 173 /* Using standard mode which the speed up to 100Kb/s */
 174 #define CONFIG_SYS_I2C_SPEED            100000
 175 #define CONFIG_SYS_I2C_SPEED1           100000
 176 #define CONFIG_SYS_I2C_SPEED2           100000
 177 #define CONFIG_SYS_I2C_SPEED3           100000
 178 /* Address of device when used as slave */
 179 #define CONFIG_SYS_I2C_SLAVE            0x02
 180 #define CONFIG_SYS_I2C_SLAVE1           0x02
 181 #define CONFIG_SYS_I2C_SLAVE2           0x02
 182 #define CONFIG_SYS_I2C_SLAVE3           0x02
 183 #ifndef __ASSEMBLY__
 184 /* Clock supplied to I2C controller in unit of MHz */
 185 unsigned int cm_get_l4_sp_clk_hz(void);
 186 #define IC_CLK                          (cm_get_l4_sp_clk_hz() / 1000000)
 187 #endif
 188 #define CONFIG_CMD_I2C
 189
 190 /*
 191  * QSPI support
 192  */
 193 /* Enable multiple SPI NOR flash manufacturers */
 194 #ifndef CONFIG_SPL_BUILD
 195 #define CONFIG_SPI_FLASH_MTD
 196 #define CONFIG_CMD_MTDPARTS
 197 #define CONFIG_MTD_DEVICE
 198 #define CONFIG_MTD_PARTITIONS
 199 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
 200 #endif
 201 /* QSPI reference clock */
 202 #ifndef __ASSEMBLY__
 203 unsigned int cm_get_qspi_controller_clk_hz(void);
 204 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
 205 #endif
 206 #define CONFIG_CQSPI_DECODER            0
 207 #define CONFIG_CMD_SF
 208 #define CONFIG_SPI_FLASH_BAR
 209
 210 /*
 211  * Designware SPI support
 212  */
 213 #define CONFIG_CMD_SPI
 214
 215 /*
 216  * Serial Driver
 217  */
 218 #define CONFIG_SYS_NS16550_SERIAL
 219 #define CONFIG_SYS_NS16550_REG_SIZE     -4
 220 #define CONFIG_SYS_NS16550_COM1         SOCFPGA_UART0_ADDRESS
 221 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 222 #define CONFIG_SYS_NS16550_CLK          1000000
 223 #else
 224 #define CONFIG_SYS_NS16550_CLK          100000000
 225 #endif
 226 #define CONFIG_CONS_INDEX               1
 227 #define CONFIG_BAUDRATE                 115200
 228
 229 /*
 230  * USB
 231  */
 232 #ifdef CONFIG_CMD_USB
 233 #define CONFIG_USB_DWC2
 234 #define CONFIG_USB_STORAGE
 235 #endif
 236
 237 /*
 238  * USB Gadget (DFU, UMS)
 239  */
 240 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
 241 #define CONFIG_USB_GADGET
 242 #define CONFIG_USB_GADGET_DWC2_OTG
 243 #define CONFIG_USB_GADGET_DUALSPEED
 244 #define CONFIG_USB_GADGET_VBUS_DRAW     2
 245
 246 /* USB Composite download gadget - g_dnl */
 247 #define CONFIG_USB_GADGET_DOWNLOAD
 248 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 249
 250 #define CONFIG_USB_FUNCTION_DFU
 251 #define CONFIG_DFU_MMC
 252 #define CONFIG_SYS_DFU_DATA_BUF_SIZE    (32 * 1024 * 1024)
 253 #define DFU_DEFAULT_POLL_TIMEOUT        300
 254
 255 /* USB IDs */
 256 #define CONFIG_G_DNL_VENDOR_NUM         0x0525  /* NetChip */
 257 #define CONFIG_G_DNL_PRODUCT_NUM        0xA4A5  /* Linux-USB File-backed Storage Gadget */
 258 #define CONFIG_G_DNL_UMS_VENDOR_NUM     CONFIG_G_DNL_VENDOR_NUM
 259 #define CONFIG_G_DNL_UMS_PRODUCT_NUM    CONFIG_G_DNL_PRODUCT_NUM
 260 #ifndef CONFIG_G_DNL_MANUFACTURER
 261 #define CONFIG_G_DNL_MANUFACTURER       CONFIG_SYS_VENDOR
 262 #endif
 263 #endif
 264
 265 /*
 266  * U-Boot environment
 267  */
 268 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 269 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 270 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 271 #define CONFIG_ENV_SIZE                 4096
 272
 273 /* Environment for SDMMC boot */
 274 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
 275 #define CONFIG_SYS_MMC_ENV_DEV          0       /* device 0 */
 276 #define CONFIG_ENV_OFFSET               512     /* just after the MBR */
 277 #endif
 278
 279 /*
 280  * mtd partitioning for serial NOR flash
 281  *
 282  * device nor0 <ff705000.spi.0>, # parts = 6
 283  * #: name                size            offset          mask_flags
 284  * 0: u-boot              0x00100000      0x00000000      0
 285  * 1: env1                0x00040000      0x00100000      0
 286  * 2: env2                0x00040000      0x00140000      0
 287  * 3: UBI                 0x03e80000      0x00180000      0
 288  * 4: boot                0x00e80000      0x00180000      0
 289  * 5: rootfs              0x01000000      0x01000000      0
 290  *
 291  */
 292 #if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT)
 293 #define MTDPARTS_DEFAULT        "mtdparts=ff705000.spi.0:"\
 294                                 "1m(u-boot),"           \
 295                                 "256k(env1),"           \
 296                                 "256k(env2),"           \
 297                                 "14848k(boot),"         \
 298                                 "16m(rootfs),"          \
 299                                 "-@1536k(UBI)\0"
 300 #endif
 301
 302 /* UBI and UBIFS support */
 303 #if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND)
 304 #define CONFIG_CMD_UBI
 305 #define CONFIG_CMD_UBIFS
 306 #define CONFIG_RBTREE
 307 #define CONFIG_LZO
 308 #endif
 309
 310 /*
 311  * SPL
 312  *
 313  * SRAM Memory layout:
 314  *
 315  * 0xFFFF_0000 ...... Start of SRAM
 316  * 0xFFFF_xxxx ...... Top of stack (grows down)
 317  * 0xFFFF_yyyy ...... Malloc area
 318  * 0xFFFF_zzzz ...... Global Data
 319  * 0xFFFF_FF00 ...... End of SRAM
 320  */
 321 #define CONFIG_SPL_FRAMEWORK
 322 #define CONFIG_SPL_RAM_DEVICE
 323 #define CONFIG_SPL_TEXT_BASE            CONFIG_SYS_INIT_RAM_ADDR
 324 #define CONFIG_SPL_MAX_SIZE             (64 * 1024)
 325 #ifdef CONFIG_SPL_BUILD
 326 #define CONFIG_SYS_MALLOC_SIMPLE
 327 #endif
 328
 329 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 330 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 331 #define CONFIG_SPL_WATCHDOG_SUPPORT
 332 #define CONFIG_SPL_SERIAL_SUPPORT
 333 #ifdef CONFIG_DM_MMC
 334 #define CONFIG_SPL_MMC_SUPPORT
 335 #endif
 336 #ifdef CONFIG_DM_SPI
 337 #define CONFIG_SPL_SPI_SUPPORT
 338 #endif
 339
 340 /* SPL SDMMC boot support */
 341 #ifdef CONFIG_SPL_MMC_SUPPORT
 342 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
 343 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      2
 344 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot-dtb.img"
 345 #define CONFIG_SPL_LIBDISK_SUPPORT
 346 #else
 347 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      3
 348 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */
 349 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS      800 /* 400 KB */
 350 #endif
 351 #endif
 352
 353 /* SPL QSPI boot support */
 354 #ifdef CONFIG_SPL_SPI_SUPPORT
 355 #define CONFIG_DM_SEQ_ALIAS             1
 356 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 357 #define CONFIG_SPL_SPI_LOAD
 358 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x40000
 359 #endif
 360
 361 /*
 362  * Stack setup
 363  */
 364 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 365
 366 #endif  /* __CONFIG_SOCFPGA_COMMON_H__ */