arm: socfpga: allow configs without network support
[platform/kernel/u-boot.git] / include / configs / socfpga_common.h
1 /*
2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 #ifndef __CONFIG_SOCFPGA_COMMON_H__
7 #define __CONFIG_SOCFPGA_COMMON_H__
8
9 /* Virtual target or real hardware */
10 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
11
12 /*
13  * High level configuration
14  */
15 #define CONFIG_DISPLAY_BOARDINFO_LATE
16 #define CONFIG_CLOCKS
17
18 #define CONFIG_SYS_BOOTMAPSZ            (64 * 1024 * 1024)
19
20 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
21
22 /* add target to build it automatically upon "make" */
23 #define CONFIG_BUILD_TARGET             "u-boot-with-spl.sfp"
24
25 /*
26  * Memory configurations
27  */
28 #define CONFIG_NR_DRAM_BANKS            1
29 #define PHYS_SDRAM_1                    0x0
30 #define CONFIG_SYS_MALLOC_LEN           (64 * 1024 * 1024)
31 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_1
32 #define CONFIG_SYS_MEMTEST_END          PHYS_SDRAM_1_SIZE
33 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
34 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFFF0000
35 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
36 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
37 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
38 #define CONFIG_SYS_INIT_RAM_SIZE        0x40000 /* 256KB */
39 #endif
40 #define CONFIG_SYS_INIT_SP_OFFSET               \
41         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
42 #define CONFIG_SYS_INIT_SP_ADDR                 \
43         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
44
45 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
46 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
47 #define CONFIG_SYS_TEXT_BASE            0x08000040
48 #else
49 #define CONFIG_SYS_TEXT_BASE            0x01000040
50 #endif
51
52 /*
53  * U-Boot general configurations
54  */
55 #define CONFIG_SYS_LONGHELP
56 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O buffer size */
57                                                 /* Print buffer size */
58 #define CONFIG_SYS_MAXARGS      32              /* Max number of command args */
59 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
60                                                 /* Boot argument buffer size */
61 #define CONFIG_AUTO_COMPLETE                    /* Command auto complete */
62 #define CONFIG_CMDLINE_EDITING                  /* Command history etc */
63
64 #ifndef CONFIG_SYS_HOSTNAME
65 #define CONFIG_SYS_HOSTNAME     CONFIG_SYS_BOARD
66 #endif
67
68 /*
69  * Cache
70  */
71 #define CONFIG_SYS_L2_PL310
72 #define CONFIG_SYS_PL310_BASE           SOCFPGA_MPUL2_ADDRESS
73
74 /*
75  * EPCS/EPCQx1 Serial Flash Controller
76  */
77 #ifdef CONFIG_ALTERA_SPI
78 #define CONFIG_SF_DEFAULT_SPEED         30000000
79 /*
80  * The base address is configurable in QSys, each board must specify the
81  * base address based on it's particular FPGA configuration. Please note
82  * that the address here is incremented by  0x400  from the Base address
83  * selected in QSys, since the SPI registers are at offset +0x400.
84  * #define CONFIG_SYS_SPI_BASE          0xff240400
85  */
86 #endif
87
88 /*
89  * Ethernet on SoC (EMAC)
90  */
91 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
92 #define CONFIG_DW_ALTDESCRIPTOR
93 #define CONFIG_MII
94 #endif
95
96 /*
97  * FPGA Driver
98  */
99 #ifdef CONFIG_CMD_FPGA
100 #define CONFIG_FPGA_COUNT               1
101 #endif
102
103 /*
104  * L4 OSC1 Timer 0
105  */
106 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
107 #define CONFIG_SYS_TIMERBASE            SOCFPGA_OSC1TIMER0_ADDRESS
108 #define CONFIG_SYS_TIMER_COUNTS_DOWN
109 #define CONFIG_SYS_TIMER_COUNTER        (CONFIG_SYS_TIMERBASE + 0x4)
110 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
111 #define CONFIG_SYS_TIMER_RATE           2400000
112 #else
113 #define CONFIG_SYS_TIMER_RATE           25000000
114 #endif
115
116 /*
117  * L4 Watchdog
118  */
119 #ifdef CONFIG_HW_WATCHDOG
120 #define CONFIG_DESIGNWARE_WATCHDOG
121 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
122 #define CONFIG_DW_WDT_CLOCK_KHZ         25000
123 #define CONFIG_WATCHDOG_TIMEOUT_MSECS   30000
124 #endif
125
126 /*
127  * MMC Driver
128  */
129 #ifdef CONFIG_CMD_MMC
130 #define CONFIG_BOUNCE_BUFFER
131 /* FIXME */
132 /* using smaller max blk cnt to avoid flooding the limited stack we have */
133 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256     /* FIXME -- SPL only? */
134 #endif
135
136 /*
137  * NAND Support
138  */
139 #ifdef CONFIG_NAND_DENALI
140 #define CONFIG_SYS_MAX_NAND_DEVICE      1
141 #define CONFIG_SYS_NAND_ONFI_DETECTION
142 #define CONFIG_SYS_NAND_REGS_BASE       SOCFPGA_NANDREGS_ADDRESS
143 #define CONFIG_SYS_NAND_DATA_BASE       SOCFPGA_NANDDATA_ADDRESS
144 #endif
145
146 /*
147  * I2C support
148  */
149 #define CONFIG_SYS_I2C
150 #define CONFIG_SYS_I2C_BASE             SOCFPGA_I2C0_ADDRESS
151 #define CONFIG_SYS_I2C_BASE1            SOCFPGA_I2C1_ADDRESS
152 #define CONFIG_SYS_I2C_BASE2            SOCFPGA_I2C2_ADDRESS
153 #define CONFIG_SYS_I2C_BASE3            SOCFPGA_I2C3_ADDRESS
154 /* Using standard mode which the speed up to 100Kb/s */
155 #define CONFIG_SYS_I2C_SPEED            100000
156 #define CONFIG_SYS_I2C_SPEED1           100000
157 #define CONFIG_SYS_I2C_SPEED2           100000
158 #define CONFIG_SYS_I2C_SPEED3           100000
159 /* Address of device when used as slave */
160 #define CONFIG_SYS_I2C_SLAVE            0x02
161 #define CONFIG_SYS_I2C_SLAVE1           0x02
162 #define CONFIG_SYS_I2C_SLAVE2           0x02
163 #define CONFIG_SYS_I2C_SLAVE3           0x02
164 #ifndef __ASSEMBLY__
165 /* Clock supplied to I2C controller in unit of MHz */
166 unsigned int cm_get_l4_sp_clk_hz(void);
167 #define IC_CLK                          (cm_get_l4_sp_clk_hz() / 1000000)
168 #endif
169
170 /*
171  * QSPI support
172  */
173 /* Enable multiple SPI NOR flash manufacturers */
174 #ifndef CONFIG_SPL_BUILD
175 #define CONFIG_SPI_FLASH_MTD
176 #define CONFIG_MTD_DEVICE
177 #define CONFIG_MTD_PARTITIONS
178 #endif
179 /* QSPI reference clock */
180 #ifndef __ASSEMBLY__
181 unsigned int cm_get_qspi_controller_clk_hz(void);
182 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
183 #endif
184 #define CONFIG_CQSPI_DECODER            0
185 #define CONFIG_BOUNCE_BUFFER
186
187 /*
188  * Designware SPI support
189  */
190
191 /*
192  * Serial Driver
193  */
194 #define CONFIG_SYS_NS16550_SERIAL
195 #define CONFIG_SYS_NS16550_REG_SIZE     -4
196 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
197 #define CONFIG_SYS_NS16550_CLK          1000000
198 #elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
199 #define CONFIG_SYS_NS16550_COM1         SOCFPGA_UART0_ADDRESS
200 #define CONFIG_SYS_NS16550_CLK          100000000
201 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
202 #define CONFIG_SYS_NS16550_COM1        SOCFPGA_UART1_ADDRESS
203 #define CONFIG_SYS_NS16550_CLK          50000000
204 #endif
205 #define CONFIG_CONS_INDEX               1
206
207 /*
208  * USB
209  */
210
211 /*
212  * USB Gadget (DFU, UMS)
213  */
214 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
215 #define CONFIG_USB_FUNCTION_MASS_STORAGE
216
217 #define CONFIG_SYS_DFU_DATA_BUF_SIZE    (16 * 1024 * 1024)
218 #define DFU_DEFAULT_POLL_TIMEOUT        300
219
220 /* USB IDs */
221 #define CONFIG_G_DNL_UMS_VENDOR_NUM     0x0525
222 #define CONFIG_G_DNL_UMS_PRODUCT_NUM    0xA4A5
223 #endif
224
225 /*
226  * U-Boot environment
227  */
228 #if !defined(CONFIG_ENV_SIZE)
229 #define CONFIG_ENV_SIZE                 (8 * 1024)
230 #endif
231
232 /* Environment for SDMMC boot */
233 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
234 #define CONFIG_SYS_MMC_ENV_DEV          0 /* device 0 */
235 #define CONFIG_ENV_OFFSET               (34 * 512) /* just after the GPT */
236 #endif
237
238 /* Environment for QSPI boot */
239 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
240 #define CONFIG_ENV_OFFSET               0x00100000
241 #define CONFIG_ENV_SECT_SIZE            (64 * 1024)
242 #endif
243
244 /*
245  * mtd partitioning for serial NOR flash
246  *
247  * device nor0 <ff705000.spi.0>, # parts = 6
248  * #: name                size            offset          mask_flags
249  * 0: u-boot              0x00100000      0x00000000      0
250  * 1: env1                0x00040000      0x00100000      0
251  * 2: env2                0x00040000      0x00140000      0
252  * 3: UBI                 0x03e80000      0x00180000      0
253  * 4: boot                0x00e80000      0x00180000      0
254  * 5: rootfs              0x01000000      0x01000000      0
255  *
256  */
257
258 /*
259  * SPL
260  *
261  * SRAM Memory layout:
262  *
263  * 0xFFFF_0000 ...... Start of SRAM
264  * 0xFFFF_xxxx ...... Top of stack (grows down)
265  * 0xFFFF_yyyy ...... Malloc area
266  * 0xFFFF_zzzz ...... Global Data
267  * 0xFFFF_FF00 ...... End of SRAM
268  */
269 #define CONFIG_SPL_FRAMEWORK
270 #define CONFIG_SPL_TEXT_BASE            CONFIG_SYS_INIT_RAM_ADDR
271 #define CONFIG_SPL_MAX_SIZE             CONFIG_SYS_INIT_RAM_SIZE
272
273 /* SPL SDMMC boot support */
274 #ifdef CONFIG_SPL_MMC_SUPPORT
275 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
276 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot-dtb.img"
277 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
278 #endif
279 #else
280 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
281 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION      1
282 #endif
283 #endif
284
285 /* SPL QSPI boot support */
286 #ifdef CONFIG_SPL_SPI_SUPPORT
287 #define CONFIG_SPL_SPI_LOAD
288 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x40000
289 #endif
290
291 /* SPL NAND boot support */
292 #ifdef CONFIG_SPL_NAND_SUPPORT
293 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
294 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
295 #endif
296
297 /*
298  * Stack setup
299  */
300 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
301
302 /* Extra Environment */
303 #ifndef CONFIG_SPL_BUILD
304 #include <config_distro_defaults.h>
305
306 #ifdef CONFIG_CMD_DHCP
307 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
308 #else
309 #define BOOT_TARGET_DEVICES_DHCP(func)
310 #endif
311
312 #ifdef CONFIG_CMD_PXE
313 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
314 #else
315 #define BOOT_TARGET_DEVICES_PXE(func)
316 #endif
317
318 #ifdef CONFIG_CMD_MMC
319 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
320 #else
321 #define BOOT_TARGET_DEVICES_MMC(func)
322 #endif
323
324 #define BOOT_TARGET_DEVICES(func) \
325         BOOT_TARGET_DEVICES_MMC(func) \
326         BOOT_TARGET_DEVICES_PXE(func) \
327         BOOT_TARGET_DEVICES_DHCP(func)
328
329 #include <config_distro_bootcmd.h>
330
331 #ifndef CONFIG_EXTRA_ENV_SETTINGS
332 #define CONFIG_EXTRA_ENV_SETTINGS \
333         "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
334         "bootm_size=0xa000000\0" \
335         "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
336         "fdt_addr_r=0x02000000\0" \
337         "scriptaddr=0x02100000\0" \
338         "pxefile_addr_r=0x02200000\0" \
339         "ramdisk_addr_r=0x02300000\0" \
340         BOOTENV
341
342 #endif
343 #endif
344
345 #endif  /* __CONFIG_SOCFPGA_COMMON_H__ */