include/configs/socfpga_common.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   4  */
   5 #ifndef __CONFIG_SOCFPGA_COMMON_H__
   6 #define __CONFIG_SOCFPGA_COMMON_H__
   7
   8 /* Virtual target or real hardware */
   9 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
  10
  11 /*
  12  * High level configuration
  13  */
  14 #define CONFIG_CLOCKS
  15
  16 #define CONFIG_SYS_BOOTMAPSZ            (64 * 1024 * 1024)
  17
  18 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  19
  20 /* add target to build it automatically upon "make" */
  21 #define CONFIG_BUILD_TARGET             "u-boot-with-spl.sfp"
  22
  23 /*
  24  * Memory configurations
  25  */
  26 #define CONFIG_NR_DRAM_BANKS            1
  27 #define PHYS_SDRAM_1                    0x0
  28 #define CONFIG_SYS_MALLOC_LEN           (64 * 1024 * 1024)
  29 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_1
  30 #define CONFIG_SYS_MEMTEST_END          PHYS_SDRAM_1_SIZE
  31 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  32 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFFF0000
  33 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
  34 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
  35 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
  36 #define CONFIG_SYS_INIT_RAM_SIZE        0x40000 /* 256KB */
  37 #endif
  38 #define CONFIG_SYS_INIT_SP_ADDR                 \
  39         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
  40
  41 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  42
  43 /*
  44  * U-Boot general configurations
  45  */
  46 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O buffer size */
  47                                                 /* Print buffer size */
  48 #define CONFIG_SYS_MAXARGS      32              /* Max number of command args */
  49 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  50                                                 /* Boot argument buffer size */
  51
  52 #ifndef CONFIG_SYS_HOSTNAME
  53 #define CONFIG_SYS_HOSTNAME     CONFIG_SYS_BOARD
  54 #endif
  55
  56 /*
  57  * Cache
  58  */
  59 #define CONFIG_SYS_L2_PL310
  60 #define CONFIG_SYS_PL310_BASE           SOCFPGA_MPUL2_ADDRESS
  61
  62 /*
  63  * EPCS/EPCQx1 Serial Flash Controller
  64  */
  65 #ifdef CONFIG_ALTERA_SPI
  66 #define CONFIG_SF_DEFAULT_SPEED         30000000
  67 /*
  68  * The base address is configurable in QSys, each board must specify the
  69  * base address based on it's particular FPGA configuration. Please note
  70  * that the address here is incremented by  0x400  from the Base address
  71  * selected in QSys, since the SPI registers are at offset +0x400.
  72  * #define CONFIG_SYS_SPI_BASE          0xff240400
  73  */
  74 #endif
  75
  76 /*
  77  * Ethernet on SoC (EMAC)
  78  */
  79 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
  80 #define CONFIG_DW_ALTDESCRIPTOR
  81 #define CONFIG_MII
  82 #endif
  83
  84 /*
  85  * FPGA Driver
  86  */
  87 #ifdef CONFIG_CMD_FPGA
  88 #define CONFIG_FPGA_COUNT               1
  89 #endif
  90
  91 /*
  92  * L4 OSC1 Timer 0
  93  */
  94 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
  95 #define CONFIG_SYS_TIMERBASE            SOCFPGA_OSC1TIMER0_ADDRESS
  96 #define CONFIG_SYS_TIMER_COUNTS_DOWN
  97 #define CONFIG_SYS_TIMER_COUNTER        (CONFIG_SYS_TIMERBASE + 0x4)
  98 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  99 #define CONFIG_SYS_TIMER_RATE           2400000
 100 #else
 101 #define CONFIG_SYS_TIMER_RATE           25000000
 102 #endif
 103
 104 /*
 105  * L4 Watchdog
 106  */
 107 #ifdef CONFIG_HW_WATCHDOG
 108 #define CONFIG_DESIGNWARE_WATCHDOG
 109 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 110 #define CONFIG_DW_WDT_CLOCK_KHZ         25000
 111 #define CONFIG_WATCHDOG_TIMEOUT_MSECS   30000
 112 #endif
 113
 114 /*
 115  * MMC Driver
 116  */
 117 #ifdef CONFIG_CMD_MMC
 118 #define CONFIG_BOUNCE_BUFFER
 119 /* FIXME */
 120 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 121 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256     /* FIXME -- SPL only? */
 122 #endif
 123
 124 /*
 125  * NAND Support
 126  */
 127 #ifdef CONFIG_NAND_DENALI
 128 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 129 #define CONFIG_SYS_NAND_ONFI_DETECTION
 130 #define CONFIG_SYS_NAND_REGS_BASE       SOCFPGA_NANDREGS_ADDRESS
 131 #define CONFIG_SYS_NAND_DATA_BASE       SOCFPGA_NANDDATA_ADDRESS
 132 #endif
 133
 134 /*
 135  * I2C support
 136  */
 137 #ifndef CONFIG_DM_I2C
 138 #define CONFIG_SYS_I2C
 139 #define CONFIG_SYS_I2C_BASE             SOCFPGA_I2C0_ADDRESS
 140 #define CONFIG_SYS_I2C_BASE1            SOCFPGA_I2C1_ADDRESS
 141 #define CONFIG_SYS_I2C_BASE2            SOCFPGA_I2C2_ADDRESS
 142 #define CONFIG_SYS_I2C_BASE3            SOCFPGA_I2C3_ADDRESS
 143 /* Using standard mode which the speed up to 100Kb/s */
 144 #define CONFIG_SYS_I2C_SPEED            100000
 145 #define CONFIG_SYS_I2C_SPEED1           100000
 146 #define CONFIG_SYS_I2C_SPEED2           100000
 147 #define CONFIG_SYS_I2C_SPEED3           100000
 148 /* Address of device when used as slave */
 149 #define CONFIG_SYS_I2C_SLAVE            0x02
 150 #define CONFIG_SYS_I2C_SLAVE1           0x02
 151 #define CONFIG_SYS_I2C_SLAVE2           0x02
 152 #define CONFIG_SYS_I2C_SLAVE3           0x02
 153 #ifndef __ASSEMBLY__
 154 /* Clock supplied to I2C controller in unit of MHz */
 155 unsigned int cm_get_l4_sp_clk_hz(void);
 156 #define IC_CLK                          (cm_get_l4_sp_clk_hz() / 1000000)
 157 #endif
 158 #endif /* CONFIG_DM_I2C */
 159
 160 /*
 161  * QSPI support
 162  */
 163 /* Enable multiple SPI NOR flash manufacturers */
 164 #ifndef CONFIG_SPL_BUILD
 165 #define CONFIG_SPI_FLASH_MTD
 166 #define CONFIG_MTD_DEVICE
 167 #define CONFIG_MTD_PARTITIONS
 168 #endif
 169 /* QSPI reference clock */
 170 #ifndef __ASSEMBLY__
 171 unsigned int cm_get_qspi_controller_clk_hz(void);
 172 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
 173 #endif
 174
 175 /*
 176  * Designware SPI support
 177  */
 178
 179 /*
 180  * Serial Driver
 181  */
 182 #define CONFIG_SYS_NS16550_SERIAL
 183 #define CONFIG_SYS_NS16550_REG_SIZE     -4
 184 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 185 #define CONFIG_SYS_NS16550_CLK          1000000
 186 #elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
 187 #define CONFIG_SYS_NS16550_COM1         SOCFPGA_UART0_ADDRESS
 188 #define CONFIG_SYS_NS16550_CLK          100000000
 189 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 190 #define CONFIG_SYS_NS16550_COM1        SOCFPGA_UART1_ADDRESS
 191 #define CONFIG_SYS_NS16550_CLK          50000000
 192 #endif
 193
 194 /*
 195  * USB
 196  */
 197
 198 /*
 199  * USB Gadget (DFU, UMS)
 200  */
 201 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
 202 #define CONFIG_SYS_DFU_DATA_BUF_SIZE    (16 * 1024 * 1024)
 203 #define DFU_DEFAULT_POLL_TIMEOUT        300
 204
 205 /* USB IDs */
 206 #define CONFIG_G_DNL_UMS_VENDOR_NUM     0x0525
 207 #define CONFIG_G_DNL_UMS_PRODUCT_NUM    0xA4A5
 208 #endif
 209
 210 /*
 211  * U-Boot environment
 212  */
 213 #if !defined(CONFIG_ENV_SIZE)
 214 #define CONFIG_ENV_SIZE                 (8 * 1024)
 215 #endif
 216
 217 /* Environment for SDMMC boot */
 218 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
 219 #define CONFIG_SYS_MMC_ENV_DEV          0 /* device 0 */
 220 #define CONFIG_ENV_OFFSET               (34 * 512) /* just after the GPT */
 221 #endif
 222
 223 /* Environment for QSPI boot */
 224 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
 225 #define CONFIG_ENV_OFFSET               0x00100000
 226 #define CONFIG_ENV_SECT_SIZE            (64 * 1024)
 227 #endif
 228
 229 /*
 230  * mtd partitioning for serial NOR flash
 231  *
 232  * device nor0 <ff705000.spi.0>, # parts = 6
 233  * #: name                size            offset          mask_flags
 234  * 0: u-boot              0x00100000      0x00000000      0
 235  * 1: env1                0x00040000      0x00100000      0
 236  * 2: env2                0x00040000      0x00140000      0
 237  * 3: UBI                 0x03e80000      0x00180000      0
 238  * 4: boot                0x00e80000      0x00180000      0
 239  * 5: rootfs              0x01000000      0x01000000      0
 240  *
 241  */
 242
 243 /*
 244  * SPL
 245  *
 246  * SRAM Memory layout:
 247  *
 248  * 0xFFFF_0000 ...... Start of SRAM
 249  * 0xFFFF_xxxx ...... Top of stack (grows down)
 250  * 0xFFFF_yyyy ...... Malloc area
 251  * 0xFFFF_zzzz ...... Global Data
 252  * 0xFFFF_FF00 ...... End of SRAM
 253  */
 254 #define CONFIG_SPL_TEXT_BASE            CONFIG_SYS_INIT_RAM_ADDR
 255 #define CONFIG_SPL_MAX_SIZE             CONFIG_SYS_INIT_RAM_SIZE
 256
 257 /* SPL SDMMC boot support */
 258 #ifdef CONFIG_SPL_MMC_SUPPORT
 259 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
 260 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot-dtb.img"
 261 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 262 #endif
 263 #else
 264 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
 265 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION      1
 266 #endif
 267 #endif
 268
 269 /* SPL QSPI boot support */
 270 #ifdef CONFIG_SPL_SPI_SUPPORT
 271 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x40000
 272 #endif
 273
 274 /* SPL NAND boot support */
 275 #ifdef CONFIG_SPL_NAND_SUPPORT
 276 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 277 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
 278 #endif
 279
 280 /*
 281  * Stack setup
 282  */
 283 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 284
 285 /* Extra Environment */
 286 #ifndef CONFIG_SPL_BUILD
 287
 288 #ifdef CONFIG_CMD_DHCP
 289 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
 290 #else
 291 #define BOOT_TARGET_DEVICES_DHCP(func)
 292 #endif
 293
 294 #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
 295 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
 296 #else
 297 #define BOOT_TARGET_DEVICES_PXE(func)
 298 #endif
 299
 300 #ifdef CONFIG_CMD_MMC
 301 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
 302 #else
 303 #define BOOT_TARGET_DEVICES_MMC(func)
 304 #endif
 305
 306 #define BOOT_TARGET_DEVICES(func) \
 307         BOOT_TARGET_DEVICES_MMC(func) \
 308         BOOT_TARGET_DEVICES_PXE(func) \
 309         BOOT_TARGET_DEVICES_DHCP(func)
 310
 311 #include <config_distro_bootcmd.h>
 312
 313 #ifndef CONFIG_EXTRA_ENV_SETTINGS
 314 #define CONFIG_EXTRA_ENV_SETTINGS \
 315         "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 316         "bootm_size=0xa000000\0" \
 317         "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
 318         "fdt_addr_r=0x02000000\0" \
 319         "scriptaddr=0x02100000\0" \
 320         "pxefile_addr_r=0x02200000\0" \
 321         "ramdisk_addr_r=0x02300000\0" \
 322         BOOTENV
 323
 324 #endif
 325 #endif
 326
 327 #endif  /* __CONFIG_SOCFPGA_COMMON_H__ */