1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
5 #ifndef __CONFIG_SOCFPGA_COMMON_H__
6 #define __CONFIG_SOCFPGA_COMMON_H__
8 #include <linux/stringify.h>
11 * Memory configurations
13 #define PHYS_SDRAM_1 0x0
14 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
15 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
16 #define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
17 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
18 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
19 /* SPL memory allocation configuration, this is for FAT implementation */
20 #ifndef CONFIG_SYS_SPL_MALLOC_SIZE
21 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000
23 #define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
24 CONFIG_SYS_SPL_MALLOC_SIZE)
25 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \
26 CONFIG_SYS_INIT_RAM_SIZE)
30 * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
31 * SRAM as bootcounter storage. Make sure to not put the stack directly
32 * at this address to not overwrite the bootcounter by checking, if the
33 * bootcounter address is located in the internal SRAM.
35 #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
36 (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
37 CONFIG_SYS_INIT_RAM_SIZE)))
38 #define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR
40 #define CONFIG_SPL_STACK \
41 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
45 * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
46 * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
47 * in U-Boot pre-reloc is higher than in SPL.
50 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
53 * U-Boot general configurations
55 /* Print buffer size */
60 #define CONFIG_SYS_L2_PL310
61 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
64 * Ethernet on SoC (EMAC)
67 #define CONFIG_DW_ALTDESCRIPTOR
73 #ifdef CONFIG_CMD_FPGA
74 #define CONFIG_FPGA_COUNT 1
81 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
82 #define CONFIG_SYS_TIMER_COUNTS_DOWN
83 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
84 #ifndef CONFIG_SYS_TIMER_RATE
85 #define CONFIG_SYS_TIMER_RATE 25000000
92 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
93 #define CONFIG_DW_WDT_CLOCK_KHZ 25000
100 /* using smaller max blk cnt to avoid flooding the limited stack we have */
101 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
107 #ifdef CONFIG_NAND_DENALI
108 #define CONFIG_SYS_MAX_NAND_DEVICE 1
109 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
110 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
118 * USB Gadget (DFU, UMS)
120 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
121 #define DFU_DEFAULT_POLL_TIMEOUT 300
124 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
125 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
132 /* Environment for SDMMC boot */
134 /* Environment for QSPI boot */
139 * SRAM Memory layout for gen 5:
141 * 0xFFFF_0000 ...... Start of SRAM
142 * 0xFFFF_xxxx ...... Top of stack (grows down)
143 * 0xFFFF_yyyy ...... Global Data
144 * 0xFFFF_zzzz ...... Malloc area
145 * 0xFFFF_FFFF ...... End of SRAM
147 * SRAM Memory layout for Arria 10:
148 * 0xFFE0_0000 ...... Start of SRAM (bottom)
149 * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
150 * 0xFFEy_yyyy ...... Global Data
151 * 0xFFEz_zzzz ...... Malloc area (grows up to top)
152 * 0xFFE3_FFFF ...... End of SRAM (top)
155 /* SPL QSPI boot support */
157 /* SPL NAND boot support */
159 /* Extra Environment */
160 #ifndef CONFIG_SPL_BUILD
162 #ifdef CONFIG_CMD_DHCP
163 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
165 #define BOOT_TARGET_DEVICES_DHCP(func)
168 #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
169 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
171 #define BOOT_TARGET_DEVICES_PXE(func)
174 #ifdef CONFIG_CMD_MMC
175 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
177 #define BOOT_TARGET_DEVICES_MMC(func)
180 #define BOOT_TARGET_DEVICES(func) \
181 BOOT_TARGET_DEVICES_MMC(func) \
182 BOOT_TARGET_DEVICES_PXE(func) \
183 BOOT_TARGET_DEVICES_DHCP(func)
185 #include <config_distro_bootcmd.h>
187 #ifndef CONFIG_EXTRA_ENV_SETTINGS
188 #define CONFIG_EXTRA_ENV_SETTINGS \
189 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
190 "bootm_size=0xa000000\0" \
191 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
192 "fdt_addr_r=0x02000000\0" \
193 "scriptaddr=0x02100000\0" \
194 "pxefile_addr_r=0x02200000\0" \
195 "ramdisk_addr_r=0x02300000\0" \
196 "socfpga_legacy_reset_compat=1\0" \
202 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */