include/configs/socfpga_common.h

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef __CONFIG_SOCFPGA_COMMON_H__
   7 #define __CONFIG_SOCFPGA_COMMON_H__
   8
   9 /* Virtual target or real hardware */
  10 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
  11
  12 /*
  13  * High level configuration
  14  */
  15 #define CONFIG_DISPLAY_BOARDINFO_LATE
  16 #define CONFIG_CLOCKS
  17
  18 #define CONFIG_SYS_BOOTMAPSZ            (64 * 1024 * 1024)
  19
  20 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  21
  22 /* add target to build it automatically upon "make" */
  23 #define CONFIG_BUILD_TARGET             "u-boot-with-spl.sfp"
  24
  25 /*
  26  * Memory configurations
  27  */
  28 #define CONFIG_NR_DRAM_BANKS            1
  29 #define PHYS_SDRAM_1                    0x0
  30 #define CONFIG_SYS_MALLOC_LEN           (64 * 1024 * 1024)
  31 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_1
  32 #define CONFIG_SYS_MEMTEST_END          PHYS_SDRAM_1_SIZE
  33 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  34 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFFF0000
  35 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
  36 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
  37 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
  38 #define CONFIG_SYS_INIT_RAM_SIZE        0x40000 /* 256KB */
  39 #endif
  40 #define CONFIG_SYS_INIT_SP_OFFSET               \
  41         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  42 #define CONFIG_SYS_INIT_SP_ADDR                 \
  43         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  44
  45 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  46 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  47 #define CONFIG_SYS_TEXT_BASE            0x08000040
  48 #else
  49 #define CONFIG_SYS_TEXT_BASE            0x01000040
  50 #endif
  51
  52 /*
  53  * U-Boot general configurations
  54  */
  55 #define CONFIG_SYS_LONGHELP
  56 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O buffer size */
  57                                                 /* Print buffer size */
  58 #define CONFIG_SYS_MAXARGS      32              /* Max number of command args */
  59 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  60                                                 /* Boot argument buffer size */
  61 #define CONFIG_AUTO_COMPLETE                    /* Command auto complete */
  62 #define CONFIG_CMDLINE_EDITING                  /* Command history etc */
  63
  64 #ifndef CONFIG_SYS_HOSTNAME
  65 #define CONFIG_SYS_HOSTNAME     CONFIG_SYS_BOARD
  66 #endif
  67
  68 /*
  69  * Cache
  70  */
  71 #define CONFIG_SYS_L2_PL310
  72 #define CONFIG_SYS_PL310_BASE           SOCFPGA_MPUL2_ADDRESS
  73
  74 /*
  75  * EPCS/EPCQx1 Serial Flash Controller
  76  */
  77 #ifdef CONFIG_ALTERA_SPI
  78 #define CONFIG_SF_DEFAULT_SPEED         30000000
  79 /*
  80  * The base address is configurable in QSys, each board must specify the
  81  * base address based on it's particular FPGA configuration. Please note
  82  * that the address here is incremented by  0x400  from the Base address
  83  * selected in QSys, since the SPI registers are at offset +0x400.
  84  * #define CONFIG_SYS_SPI_BASE          0xff240400
  85  */
  86 #endif
  87
  88 /*
  89  * Ethernet on SoC (EMAC)
  90  */
  91 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
  92 #define CONFIG_DW_ALTDESCRIPTOR
  93 #define CONFIG_MII
  94 #endif
  95
  96 /*
  97  * FPGA Driver
  98  */
  99 #ifdef CONFIG_CMD_FPGA
 100 #define CONFIG_FPGA_COUNT               1
 101 #endif
 102
 103 /*
 104  * L4 OSC1 Timer 0
 105  */
 106 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
 107 #define CONFIG_SYS_TIMERBASE            SOCFPGA_OSC1TIMER0_ADDRESS
 108 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 109 #define CONFIG_SYS_TIMER_COUNTER        (CONFIG_SYS_TIMERBASE + 0x4)
 110 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 111 #define CONFIG_SYS_TIMER_RATE           2400000
 112 #else
 113 #define CONFIG_SYS_TIMER_RATE           25000000
 114 #endif
 115
 116 /*
 117  * L4 Watchdog
 118  */
 119 #ifdef CONFIG_HW_WATCHDOG
 120 #define CONFIG_DESIGNWARE_WATCHDOG
 121 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 122 #define CONFIG_DW_WDT_CLOCK_KHZ         25000
 123 #define CONFIG_WATCHDOG_TIMEOUT_MSECS   30000
 124 #endif
 125
 126 /*
 127  * MMC Driver
 128  */
 129 #ifdef CONFIG_CMD_MMC
 130 #define CONFIG_BOUNCE_BUFFER
 131 /* FIXME */
 132 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 133 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256     /* FIXME -- SPL only? */
 134 #endif
 135
 136 /*
 137  * NAND Support
 138  */
 139 #ifdef CONFIG_NAND_DENALI
 140 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 141 #define CONFIG_SYS_NAND_ONFI_DETECTION
 142 #define CONFIG_SYS_NAND_REGS_BASE       SOCFPGA_NANDREGS_ADDRESS
 143 #define CONFIG_SYS_NAND_DATA_BASE       SOCFPGA_NANDDATA_ADDRESS
 144 #endif
 145
 146 /*
 147  * I2C support
 148  */
 149 #define CONFIG_SYS_I2C
 150 #define CONFIG_SYS_I2C_BASE             SOCFPGA_I2C0_ADDRESS
 151 #define CONFIG_SYS_I2C_BASE1            SOCFPGA_I2C1_ADDRESS
 152 #define CONFIG_SYS_I2C_BASE2            SOCFPGA_I2C2_ADDRESS
 153 #define CONFIG_SYS_I2C_BASE3            SOCFPGA_I2C3_ADDRESS
 154 /* Using standard mode which the speed up to 100Kb/s */
 155 #define CONFIG_SYS_I2C_SPEED            100000
 156 #define CONFIG_SYS_I2C_SPEED1           100000
 157 #define CONFIG_SYS_I2C_SPEED2           100000
 158 #define CONFIG_SYS_I2C_SPEED3           100000
 159 /* Address of device when used as slave */
 160 #define CONFIG_SYS_I2C_SLAVE            0x02
 161 #define CONFIG_SYS_I2C_SLAVE1           0x02
 162 #define CONFIG_SYS_I2C_SLAVE2           0x02
 163 #define CONFIG_SYS_I2C_SLAVE3           0x02
 164 #ifndef __ASSEMBLY__
 165 /* Clock supplied to I2C controller in unit of MHz */
 166 unsigned int cm_get_l4_sp_clk_hz(void);
 167 #define IC_CLK                          (cm_get_l4_sp_clk_hz() / 1000000)
 168 #endif
 169
 170 /*
 171  * QSPI support
 172  */
 173 /* Enable multiple SPI NOR flash manufacturers */
 174 #ifndef CONFIG_SPL_BUILD
 175 #define CONFIG_SPI_FLASH_MTD
 176 #define CONFIG_MTD_DEVICE
 177 #define CONFIG_MTD_PARTITIONS
 178 #endif
 179 /* QSPI reference clock */
 180 #ifndef __ASSEMBLY__
 181 unsigned int cm_get_qspi_controller_clk_hz(void);
 182 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
 183 #endif
 184
 185 /*
 186  * Designware SPI support
 187  */
 188
 189 /*
 190  * Serial Driver
 191  */
 192 #define CONFIG_SYS_NS16550_SERIAL
 193 #define CONFIG_SYS_NS16550_REG_SIZE     -4
 194 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 195 #define CONFIG_SYS_NS16550_CLK          1000000
 196 #elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
 197 #define CONFIG_SYS_NS16550_COM1         SOCFPGA_UART0_ADDRESS
 198 #define CONFIG_SYS_NS16550_CLK          100000000
 199 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 200 #define CONFIG_SYS_NS16550_COM1        SOCFPGA_UART1_ADDRESS
 201 #define CONFIG_SYS_NS16550_CLK          50000000
 202 #endif
 203 #define CONFIG_CONS_INDEX               1
 204
 205 /*
 206  * USB
 207  */
 208
 209 /*
 210  * USB Gadget (DFU, UMS)
 211  */
 212 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
 213 #define CONFIG_SYS_DFU_DATA_BUF_SIZE    (16 * 1024 * 1024)
 214 #define DFU_DEFAULT_POLL_TIMEOUT        300
 215
 216 /* USB IDs */
 217 #define CONFIG_G_DNL_UMS_VENDOR_NUM     0x0525
 218 #define CONFIG_G_DNL_UMS_PRODUCT_NUM    0xA4A5
 219 #endif
 220
 221 /*
 222  * U-Boot environment
 223  */
 224 #if !defined(CONFIG_ENV_SIZE)
 225 #define CONFIG_ENV_SIZE                 (8 * 1024)
 226 #endif
 227
 228 /* Environment for SDMMC boot */
 229 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
 230 #define CONFIG_SYS_MMC_ENV_DEV          0 /* device 0 */
 231 #define CONFIG_ENV_OFFSET               (34 * 512) /* just after the GPT */
 232 #endif
 233
 234 /* Environment for QSPI boot */
 235 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
 236 #define CONFIG_ENV_OFFSET               0x00100000
 237 #define CONFIG_ENV_SECT_SIZE            (64 * 1024)
 238 #endif
 239
 240 /*
 241  * mtd partitioning for serial NOR flash
 242  *
 243  * device nor0 <ff705000.spi.0>, # parts = 6
 244  * #: name                size            offset          mask_flags
 245  * 0: u-boot              0x00100000      0x00000000      0
 246  * 1: env1                0x00040000      0x00100000      0
 247  * 2: env2                0x00040000      0x00140000      0
 248  * 3: UBI                 0x03e80000      0x00180000      0
 249  * 4: boot                0x00e80000      0x00180000      0
 250  * 5: rootfs              0x01000000      0x01000000      0
 251  *
 252  */
 253
 254 /*
 255  * SPL
 256  *
 257  * SRAM Memory layout:
 258  *
 259  * 0xFFFF_0000 ...... Start of SRAM
 260  * 0xFFFF_xxxx ...... Top of stack (grows down)
 261  * 0xFFFF_yyyy ...... Malloc area
 262  * 0xFFFF_zzzz ...... Global Data
 263  * 0xFFFF_FF00 ...... End of SRAM
 264  */
 265 #define CONFIG_SPL_FRAMEWORK
 266 #define CONFIG_SPL_TEXT_BASE            CONFIG_SYS_INIT_RAM_ADDR
 267 #define CONFIG_SPL_MAX_SIZE             CONFIG_SYS_INIT_RAM_SIZE
 268
 269 /* SPL SDMMC boot support */
 270 #ifdef CONFIG_SPL_MMC_SUPPORT
 271 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
 272 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot-dtb.img"
 273 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 274 #endif
 275 #else
 276 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
 277 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION      1
 278 #endif
 279 #endif
 280
 281 /* SPL QSPI boot support */
 282 #ifdef CONFIG_SPL_SPI_SUPPORT
 283 #define CONFIG_SPL_SPI_LOAD
 284 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x40000
 285 #endif
 286
 287 /* SPL NAND boot support */
 288 #ifdef CONFIG_SPL_NAND_SUPPORT
 289 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 290 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
 291 #endif
 292
 293 /*
 294  * Stack setup
 295  */
 296 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 297
 298 /* Extra Environment */
 299 #ifndef CONFIG_SPL_BUILD
 300 #include <config_distro_defaults.h>
 301
 302 #ifdef CONFIG_CMD_DHCP
 303 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
 304 #else
 305 #define BOOT_TARGET_DEVICES_DHCP(func)
 306 #endif
 307
 308 #ifdef CONFIG_CMD_PXE
 309 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
 310 #else
 311 #define BOOT_TARGET_DEVICES_PXE(func)
 312 #endif
 313
 314 #ifdef CONFIG_CMD_MMC
 315 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
 316 #else
 317 #define BOOT_TARGET_DEVICES_MMC(func)
 318 #endif
 319
 320 #define BOOT_TARGET_DEVICES(func) \
 321         BOOT_TARGET_DEVICES_MMC(func) \
 322         BOOT_TARGET_DEVICES_PXE(func) \
 323         BOOT_TARGET_DEVICES_DHCP(func)
 324
 325 #include <config_distro_bootcmd.h>
 326
 327 #ifndef CONFIG_EXTRA_ENV_SETTINGS
 328 #define CONFIG_EXTRA_ENV_SETTINGS \
 329         "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 330         "bootm_size=0xa000000\0" \
 331         "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
 332         "fdt_addr_r=0x02000000\0" \
 333         "scriptaddr=0x02100000\0" \
 334         "pxefile_addr_r=0x02200000\0" \
 335         "ramdisk_addr_r=0x02300000\0" \
 336         BOOTENV
 337
 338 #endif
 339 #endif
 340
 341 #endif  /* __CONFIG_SOCFPGA_COMMON_H__ */