include/configs/socfpga_common.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   4  */
   5 #ifndef __CONFIG_SOCFPGA_COMMON_H__
   6 #define __CONFIG_SOCFPGA_COMMON_H__
   7
   8 #include <linux/stringify.h>
   9
  10 /*
  11  * High level configuration
  12  */
  13 #define CONFIG_CLOCKS
  14
  15 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  16
  17 /*
  18  * Memory configurations
  19  */
  20 #define PHYS_SDRAM_1                    0x0
  21 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  22 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFFF0000
  23 #define CONFIG_SYS_INIT_RAM_SIZE        SOCFPGA_PHYS_OCRAM_SIZE
  24 #define CONFIG_SPL_PAD_TO               0x10000
  25 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
  26 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
  27 #define CONFIG_SPL_PAD_TO               0x40000
  28 /* SPL memory allocation configuration, this is for FAT implementation */
  29 #ifndef CONFIG_SYS_SPL_MALLOC_SIZE
  30 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x10000
  31 #endif
  32 #define CONFIG_SYS_INIT_RAM_SIZE        (SOCFPGA_PHYS_OCRAM_SIZE - \
  33                                          CONFIG_SYS_SPL_MALLOC_SIZE)
  34 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_INIT_RAM_ADDR + \
  35                                          CONFIG_SYS_INIT_RAM_SIZE)
  36 #endif
  37
  38 /*
  39  * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
  40  * SRAM as bootcounter storage. Make sure to not put the stack directly
  41  * at this address to not overwrite the bootcounter by checking, if the
  42  * bootcounter address is located in the internal SRAM.
  43  */
  44 #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) &&  \
  45      (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR +   \
  46                                    CONFIG_SYS_INIT_RAM_SIZE)))
  47 #define CONFIG_SPL_STACK                CONFIG_SYS_BOOTCOUNT_ADDR
  48 #else
  49 #define CONFIG_SPL_STACK                        \
  50         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
  51 #endif
  52
  53 /*
  54  * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
  55  * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
  56  * in U-Boot pre-reloc is higher than in SPL.
  57  */
  58 #if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
  59 #define CONFIG_SYS_INIT_SP_ADDR         CONFIG_SPL_STACK_R_ADDR
  60 #else
  61 #define CONFIG_SYS_INIT_SP_ADDR         CONFIG_SPL_STACK
  62 #endif
  63
  64 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  65
  66 /*
  67  * U-Boot general configurations
  68  */
  69 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O buffer size */
  70                                                 /* Print buffer size */
  71 #define CONFIG_SYS_MAXARGS      32              /* Max number of command args */
  72 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  73                                                 /* Boot argument buffer size */
  74
  75 /*
  76  * Cache
  77  */
  78 #define CONFIG_SYS_L2_PL310
  79 #define CONFIG_SYS_PL310_BASE           SOCFPGA_MPUL2_ADDRESS
  80
  81 /*
  82  * Ethernet on SoC (EMAC)
  83  */
  84 #ifdef CONFIG_CMD_NET
  85 #define CONFIG_DW_ALTDESCRIPTOR
  86 #endif
  87
  88 /*
  89  * FPGA Driver
  90  */
  91 #ifdef CONFIG_CMD_FPGA
  92 #define CONFIG_FPGA_COUNT               1
  93 #endif
  94
  95 /*
  96  * L4 OSC1 Timer 0
  97  */
  98 #ifndef CONFIG_TIMER
  99 #define CONFIG_SYS_TIMERBASE            SOCFPGA_OSC1TIMER0_ADDRESS
 100 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 101 #define CONFIG_SYS_TIMER_COUNTER        (CONFIG_SYS_TIMERBASE + 0x4)
 102 #ifndef CONFIG_SYS_TIMER_RATE
 103 #define CONFIG_SYS_TIMER_RATE           25000000
 104 #endif
 105 #endif
 106
 107 /*
 108  * L4 Watchdog
 109  */
 110 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 111 #define CONFIG_DW_WDT_CLOCK_KHZ         25000
 112
 113 /*
 114  * MMC Driver
 115  */
 116 #ifdef CONFIG_CMD_MMC
 117 /* FIXME */
 118 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 119 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256     /* FIXME -- SPL only? */
 120 #endif
 121
 122 /*
 123  * NAND Support
 124  */
 125 #ifdef CONFIG_NAND_DENALI
 126 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 127 #define CONFIG_SYS_NAND_ONFI_DETECTION
 128 #define CONFIG_SYS_NAND_REGS_BASE       SOCFPGA_NANDREGS_ADDRESS
 129 #define CONFIG_SYS_NAND_DATA_BASE       SOCFPGA_NANDDATA_ADDRESS
 130 #endif
 131
 132 /*
 133  * QSPI support
 134  */
 135 /* QSPI reference clock */
 136 #ifndef __ASSEMBLY__
 137 unsigned int cm_get_qspi_controller_clk_hz(void);
 138 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
 139 #endif
 140
 141 /*
 142  * USB
 143  */
 144
 145 /*
 146  * USB Gadget (DFU, UMS)
 147  */
 148 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
 149 #define DFU_DEFAULT_POLL_TIMEOUT        300
 150
 151 /* USB IDs */
 152 #define CONFIG_G_DNL_UMS_VENDOR_NUM     0x0525
 153 #define CONFIG_G_DNL_UMS_PRODUCT_NUM    0xA4A5
 154 #endif
 155
 156 /*
 157  * U-Boot environment
 158  */
 159
 160 /* Environment for SDMMC boot */
 161
 162 /* Environment for QSPI boot */
 163
 164 /*
 165  * SPL
 166  *
 167  * SRAM Memory layout for gen 5:
 168  *
 169  * 0xFFFF_0000 ...... Start of SRAM
 170  * 0xFFFF_xxxx ...... Top of stack (grows down)
 171  * 0xFFFF_yyyy ...... Global Data
 172  * 0xFFFF_zzzz ...... Malloc area
 173  * 0xFFFF_FFFF ...... End of SRAM
 174  *
 175  * SRAM Memory layout for Arria 10:
 176  * 0xFFE0_0000 ...... Start of SRAM (bottom)
 177  * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
 178  * 0xFFEy_yyyy ...... Global Data
 179  * 0xFFEz_zzzz ...... Malloc area (grows up to top)
 180  * 0xFFE3_FFFF ...... End of SRAM (top)
 181  */
 182 #ifndef CONFIG_SPL_TEXT_BASE
 183 #define CONFIG_SPL_MAX_SIZE             CONFIG_SYS_INIT_RAM_SIZE
 184 #endif
 185
 186 /* SPL SDMMC boot support */
 187 #ifdef CONFIG_SPL_MMC
 188 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
 189 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.img"
 190 #endif
 191 #else
 192 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
 193 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION      1
 194 #endif
 195 #endif
 196
 197 /* SPL QSPI boot support */
 198
 199 /* SPL NAND boot support */
 200 #ifdef CONFIG_SPL_NAND_SUPPORT
 201 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 202 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
 203 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 204 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x100000
 205 #endif
 206 #endif
 207
 208 /* Extra Environment */
 209 #ifndef CONFIG_SPL_BUILD
 210
 211 #ifdef CONFIG_CMD_DHCP
 212 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
 213 #else
 214 #define BOOT_TARGET_DEVICES_DHCP(func)
 215 #endif
 216
 217 #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
 218 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
 219 #else
 220 #define BOOT_TARGET_DEVICES_PXE(func)
 221 #endif
 222
 223 #ifdef CONFIG_CMD_MMC
 224 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
 225 #else
 226 #define BOOT_TARGET_DEVICES_MMC(func)
 227 #endif
 228
 229 #define BOOT_TARGET_DEVICES(func) \
 230         BOOT_TARGET_DEVICES_MMC(func) \
 231         BOOT_TARGET_DEVICES_PXE(func) \
 232         BOOT_TARGET_DEVICES_DHCP(func)
 233
 234 #include <config_distro_bootcmd.h>
 235
 236 #ifndef CONFIG_EXTRA_ENV_SETTINGS
 237 #define CONFIG_EXTRA_ENV_SETTINGS \
 238         "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 239         "bootm_size=0xa000000\0" \
 240         "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
 241         "fdt_addr_r=0x02000000\0" \
 242         "scriptaddr=0x02100000\0" \
 243         "pxefile_addr_r=0x02200000\0" \
 244         "ramdisk_addr_r=0x02300000\0" \
 245         "socfpga_legacy_reset_compat=1\0" \
 246         BOOTENV
 247
 248 #endif
 249 #endif
 250
 251 #endif  /* __CONFIG_SOCFPGA_COMMON_H__ */