1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
5 #ifndef __CONFIG_SOCFPGA_COMMON_H__
6 #define __CONFIG_SOCFPGA_COMMON_H__
9 * High level configuration
13 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
16 * Memory configurations
18 #define PHYS_SDRAM_1 0x0
19 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
20 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
21 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
22 #define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
23 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
24 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
25 /* SPL memory allocation configuration, this is for FAT implementation */
26 #ifndef CONFIG_SYS_SPL_MALLOC_SIZE
27 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000
29 #define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
30 CONFIG_SYS_SPL_MALLOC_SIZE)
31 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \
32 CONFIG_SYS_INIT_RAM_SIZE)
36 * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
37 * SRAM as bootcounter storage. Make sure to not put the stack directly
38 * at this address to not overwrite the bootcounter by checking, if the
39 * bootcounter address is located in the internal SRAM.
41 #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
42 (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
43 CONFIG_SYS_INIT_RAM_SIZE)))
44 #define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR
46 #define CONFIG_SPL_STACK \
47 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
51 * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
52 * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
53 * in U-Boot pre-reloc is higher than in SPL.
55 #if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
56 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR
58 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
61 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
64 * U-Boot general configurations
66 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
67 /* Print buffer size */
68 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
69 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
70 /* Boot argument buffer size */
75 #define CONFIG_SYS_L2_PL310
76 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
79 * Ethernet on SoC (EMAC)
82 #define CONFIG_DW_ALTDESCRIPTOR
88 #ifdef CONFIG_CMD_FPGA
89 #define CONFIG_FPGA_COUNT 1
96 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
97 #define CONFIG_SYS_TIMER_COUNTS_DOWN
98 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
99 #ifndef CONFIG_SYS_TIMER_RATE
100 #define CONFIG_SYS_TIMER_RATE 25000000
107 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
108 #define CONFIG_DW_WDT_CLOCK_KHZ 25000
113 #ifdef CONFIG_CMD_MMC
115 /* using smaller max blk cnt to avoid flooding the limited stack we have */
116 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
122 #ifdef CONFIG_NAND_DENALI
123 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
124 #define CONFIG_SYS_MAX_NAND_DEVICE 1
125 #define CONFIG_SYS_NAND_ONFI_DETECTION
126 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
127 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
133 /* QSPI reference clock */
135 unsigned int cm_get_qspi_controller_clk_hz(void);
136 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
144 * USB Gadget (DFU, UMS)
146 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
147 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024)
148 #define DFU_DEFAULT_POLL_TIMEOUT 300
151 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
152 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
159 /* Environment for SDMMC boot */
160 #if defined(CONFIG_ENV_IS_IN_MMC)
161 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
164 /* Environment for QSPI boot */
169 * SRAM Memory layout for gen 5:
171 * 0xFFFF_0000 ...... Start of SRAM
172 * 0xFFFF_xxxx ...... Top of stack (grows down)
173 * 0xFFFF_yyyy ...... Global Data
174 * 0xFFFF_zzzz ...... Malloc area
175 * 0xFFFF_FFFF ...... End of SRAM
177 * SRAM Memory layout for Arria 10:
178 * 0xFFE0_0000 ...... Start of SRAM (bottom)
179 * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
180 * 0xFFEy_yyyy ...... Global Data
181 * 0xFFEz_zzzz ...... Malloc area (grows up to top)
182 * 0xFFE3_FFFF ...... End of SRAM (top)
184 #ifndef CONFIG_SPL_TEXT_BASE
185 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
188 /* SPL SDMMC boot support */
189 #ifdef CONFIG_SPL_MMC_SUPPORT
190 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
191 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
192 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
195 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
196 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
200 /* SPL QSPI boot support */
202 /* SPL NAND boot support */
203 #ifdef CONFIG_SPL_NAND_SUPPORT
204 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
205 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
206 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
207 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000
211 /* Extra Environment */
212 #ifndef CONFIG_SPL_BUILD
214 #ifdef CONFIG_CMD_DHCP
215 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
217 #define BOOT_TARGET_DEVICES_DHCP(func)
220 #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
221 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
223 #define BOOT_TARGET_DEVICES_PXE(func)
226 #ifdef CONFIG_CMD_MMC
227 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
229 #define BOOT_TARGET_DEVICES_MMC(func)
232 #define BOOT_TARGET_DEVICES(func) \
233 BOOT_TARGET_DEVICES_MMC(func) \
234 BOOT_TARGET_DEVICES_PXE(func) \
235 BOOT_TARGET_DEVICES_DHCP(func)
237 #include <config_distro_bootcmd.h>
239 #ifndef CONFIG_EXTRA_ENV_SETTINGS
240 #define CONFIG_EXTRA_ENV_SETTINGS \
241 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
242 "bootm_size=0xa000000\0" \
243 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
244 "fdt_addr_r=0x02000000\0" \
245 "scriptaddr=0x02100000\0" \
246 "pxefile_addr_r=0x02200000\0" \
247 "ramdisk_addr_r=0x02300000\0" \
248 "socfpga_legacy_reset_compat=1\0" \
254 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */