1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2022 Google LLC
5 #ifndef __SOCFGPA_CHAMELEONV3_H__
6 #define __SOCFGPA_CHAMELEONV3_H__
8 #include <asm/arch/base_addr_a10.h>
11 * U-Boot general configurations
14 /* Memory configurations */
15 #define PHYS_SDRAM_1_SIZE 0x40000000
18 * Serial / UART configurations
20 #define CONFIG_SYS_NS16550_MEM32
21 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
23 #define CONFIG_EXTRA_ENV_SETTINGS \
25 "bootargs=cma=256M console=ttyS1,115200 root=/dev/mmcblk0p3 rw rootwait\0" \
26 "distro_bootcmd=bridge enable; run bootcmd_mmc\0" \
27 "bootcmd_mmc=load mmc 0:1 ${loadaddr} kernel.itb; bootm\0" \
28 "bootcmd_net=dhcp; tftpboot ${loadaddr} kernel.itb; bootm\0"
33 /* reload value when timer count to zero */
34 #define TIMER_LOAD_VAL 0xFFFFFFFF
36 /* The rest of the configuration is shared */
37 #include <configs/socfpga_common.h>
39 #endif /* __SOCFGPA_CHAMELEONV3_H__ */