1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2017-2020 ABB
6 #ifndef __CONFIG_SOCFPGA_SECU1_H__
7 #define __CONFIG_SOCFPGA_SECU1_H__
9 #include <asm/arch/base_addr_ac5.h>
11 /* Call misc_init_r */
12 #define CONFIG_MISC_INIT_R
14 #define CONFIG_HUSH_INIT_VAR
15 /* Eternal oscillator */
16 #define CONFIG_SYS_TIMER_RATE 40000000
18 /* Memory configurations */
19 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512MiB on SECU1 */
22 * We use bootcounter in i2c nvram of the RTC (0x68)
23 * The offset fopr the bootcounter is 0x9e, which are
24 * the last two bytes of the 128 bytes large NVRAM in the
25 * RTC which begin at address 0x20
27 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
30 #define CONFIG_BOOTDELAY 2
31 #define CONFIG_BOOTFILE "zImage"
32 #define CONFIG_BOOTARGS \
33 "console=ttyS0," __stringify(CONFIG_BAUDRATE) \
34 " ubi.fm_autoconvert=1" \
35 " uio_pdrv_genirq.of_id=\"idq,regbank\""
37 #define CONFIG_BOOTCOMMAND \
40 "if test ${bootnum} = \"b\"; " \
41 "then run _fpga_loadsafe; " \
42 "else if test ${bootcount} -eq 4; then echo \"Switching copy...\"; setexpr x $bootnum % 2 && setexpr bootnum $x + 1; saveenv; fi; " \
43 "run _fpga_loaduser; " \
45 "echo \"Booting bank $bootnum\" && run userload && run userboot;" \
47 "setenv altbootcmd 'setenv bootnum b && saveenv && boot;' && " \
48 "saveenv && saveenv && boot;"
50 #define CONFIG_CMDLINE_TAG
51 #define CONFIG_SYS_BOOTM_LEN (64 << 20)
53 /* Environment settings */
54 #define CONFIG_ENV_OVERWRITE
59 * After 45s of inactivity in the prompt, the board will reset.
60 * Set 'bootretry' in the environment to -1 to disable this behavior
62 #define CONFIG_BOOT_RETRY_TIME 45
63 #define CONFIG_RESET_TO_RETRY
65 #define CONFIG_LOADADDR 0x01000000
66 #define CONFIG_SYS_LOAD_ADDR CONFIG_KM_KERNEL_ADDR
69 * FPGA Remote Update related environment
71 * Note that since those commands access the FPGA, the HPS-to-FPGA
72 * bridges MUST have been previously enabled (for example
73 * with 'bridge enable').
75 #define FPGA_RMTU_ENV \
76 "rmtu_page=0xFF29000C\0" \
77 "rmtu_reconfig=0xFF290018\0" \
78 "fpga_safebase=0x0\0" \
79 "fpga_userbase=0x2000000\0" \
80 "_fpga_loaduser=echo Loading FPGA USER image..." \
81 " && mw ${rmtu_page} ${fpga_userbase} && mw ${rmtu_reconfig} 1\0" \
82 "_fpga_loadsafe=echo Loading FPGA SAFE image..." \
83 " && mw ${rmtu_page} ${fpga_safebase} && mw ${rmtu_reconfig} 1\0" \
85 #define CONFIG_KM_NEW_ENV \
87 "nand erase 0x100000 0x40000\0"
89 #define CONFIG_KM_DEF_ENV_BOOTTARGETS \
91 "run newenv; reset\0" \
93 "tftp 0x200000 scripts/develop-secu.txt && env import -t 0x200000 ${filesize} && saveenv && reset\0"
95 #define CONFIG_EXTRA_ENV_SETTINGS \
97 CONFIG_KM_DEF_ENV_BOOTTARGETS \
99 "socfpga_legacy_reset_compat=1\0" \
100 "altbootcmd=run bootcmd;\0" \
103 "bootretry=" __stringify(CONFIG_BOOT_RETRY_TIME) "\0" \
104 "fdt_addr=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
105 "load=tftpboot ${loadaddr} u-boot-with-nand-spl.sfp\0" \
106 "loadaddr=" __stringify(CONFIG_KM_KERNEL_ADDR) "\0" \
107 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
108 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
109 "update=nand erase 0x0 0x00100000 && nand write ${loadaddr} 0x0 ${filesize}\0" \
110 "userload=ubi part nand.ubi &&" \
111 "ubi check rootfs$bootnum &&" \
112 "ubi read $fdt_addr dtb$bootnum &&" \
113 "ubi read $loadaddr kernel$bootnum\0" \
114 "userboot=setenv bootargs " CONFIG_BOOTARGS \
115 " ubi.mtd=1 ubi.block=0,rootfs$bootnum root=/dev/ubiblock0_$ubivolid" \
116 " ro rootfstype=squashfs init=sbin/preinit;" \
117 "bootz ${loadaddr} - ${fdt_addr}\0" \
120 /* The rest of the configuration is shared */
121 #include <configs/socfpga_common.h>
123 #ifdef CONFIG_SPL_NAND_SUPPORT
124 #undef CONFIG_SYS_NAND_U_BOOT_OFFS
125 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
128 #undef CONFIG_WATCHDOG_TIMEOUT_MSECS
129 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000
131 #endif /* __CONFIG_SOCFPGA_SECU1_H__ */