1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Bluewater Systems Snapper 9260 and 9G20 modules
5 * (C) Copyright 2011 Bluewater Systems
6 * Author: Andre Renaud <andre@bluewatersys.com>
7 * Author: Ryan Mallon <ryan@bluewatersys.com>
13 /* SoC type is defined in boards.cfg */
14 #include <asm/hardware.h>
15 #include <linux/sizes.h>
17 /* ARM asynchronous clock */
18 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */
19 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
22 #define CONFIG_ARCH_CPU_INIT
24 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
25 #define CONFIG_SETUP_MEMORY_TAGS
26 #define CONFIG_INITRD_TAG
27 #define CONFIG_SKIP_LOWLEVEL_INIT
30 #define CONFIG_NR_DRAM_BANKS 1
31 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
32 #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */
33 #define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \
34 GENERATED_GBL_DATA_SIZE)
36 /* Mem test settings */
37 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
38 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024))
41 #define CONFIG_SYS_MAX_NAND_DEVICE 1
42 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
43 #define CONFIG_SYS_NAND_DBW_8
44 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */
45 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */
46 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
47 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
52 #define CONFIG_NET_RETRY_COUNT 20
53 #define CONFIG_RESET_PHY_R
54 #define CONFIG_AT91_WANTS_COMMON_PHY
55 #define CONFIG_TFTP_PORT
56 #define CONFIG_TFTP_TSIZE
59 #define CONFIG_USB_ATMEL
60 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
61 #define CONFIG_USB_OHCI_NEW
62 #define CONFIG_SYS_USB_OHCI_CPU_INIT
63 #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
64 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
65 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
67 /* GPIOs and IO expander */
68 #define CONFIG_ATMEL_LEGACY
69 #define CONFIG_AT91_GPIO
70 #define CONFIG_AT91_GPIO_PULLUP 1
71 #define CONFIG_PCA953X
72 #define CONFIG_SYS_I2C_PCA953X_ADDR 0x28
73 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} }
75 /* UARTs/Serial console */
76 #define CONFIG_ATMEL_USART
77 #ifndef CONFIG_DM_SERIAL
78 #define CONFIG_USART_BASE ATMEL_BASE_DBGU
79 #define CONFIG_USART_ID ATMEL_ID_SYS
82 /* I2C - Bit-bashed */
83 #define CONFIG_SYS_I2C
84 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
85 #define CONFIG_SYS_I2C_SOFT_SPEED 100000
86 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
87 #define CONFIG_SOFT_I2C_READ_REPEATED_START
88 #define I2C_INIT do { \
89 at91_set_gpio_output(AT91_PIN_PA23, 1); \
90 at91_set_gpio_output(AT91_PIN_PA24, 1); \
91 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
92 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
94 #define I2C_SOFT_DECLARATIONS
96 #define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PA23, 1);
97 #define I2C_READ at91_get_gpio_value(AT91_PIN_PA23);
98 #define I2C_SDA(bit) do { \
100 at91_set_gpio_input(AT91_PIN_PA23, 1); \
102 at91_set_gpio_output(AT91_PIN_PA23, 1); \
103 at91_set_gpio_value(AT91_PIN_PA23, bit); \
106 #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
107 #define I2C_DELAY udelay(2)
110 #define CONFIG_SYS_LOAD_ADDR 0x23000000
112 #define CONFIG_BOOTP_BOOTFILESIZE
114 /* Environment settings */
115 #define CONFIG_ENV_OFFSET (512 << 10)
116 #define CONFIG_ENV_SIZE (256 << 10)
117 #define CONFIG_ENV_OVERWRITE
119 /* Console settings */
121 /* U-Boot memory settings */
122 #define CONFIG_SYS_MALLOC_LEN (1 << 20)
124 #endif /* __CONFIG_H */