1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
8 * Achim Ehrlich <aehrlich@taskit.de>
9 * taskit GmbH <www.taskit.de>
12 * Markus Hubig <mhubig@imko.de>
13 * IMKO GmbH <www.imko.de>
16 * Heiko Schocher <hs@denx.de>
17 * DENX Software Engineering GmbH
19 * Configuation settings for the smartweb.
26 * SoC must be defined first, before hardware.h is included.
27 * In this case SoC is defined in boards.cfg.
29 #include <asm/hardware.h>
30 #include <linux/sizes.h>
33 * Warning: changing CONFIG_TEXT_BASE requires adapting the initial boot
34 * program. Since the linker has to swallow that define, we must use a pure
38 /* ARM asynchronous clock */
39 #define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
40 #define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */
45 * SDRAM: 1 bank, 64 MB, base address 0x20000000
46 * Already initialized before u-boot gets started.
48 #define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
49 #define CFG_SYS_SDRAM_SIZE (64 * SZ_1M)
52 * Perform a SDRAM Memtest from the start of SDRAM
53 * till the beginning of the U-Boot position in RAM.
56 /* NAND flash settings */
57 #define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
58 #define CFG_SYS_NAND_MASK_ALE (1 << 21)
59 #define CFG_SYS_NAND_MASK_CLE (1 << 22)
60 #define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
61 #define CFG_SYS_NAND_READY_PIN AT91_PIN_PC13
64 #define CFG_USART_BASE ATMEL_BASE_DBGU
65 #define CFG_USART_ID ATMEL_ID_SYS
67 /* DFU class support */
68 #define DFU_MANIFEST_POLL_TIMEOUT 25000
70 /* General Boot Parameter */
73 * Predefined environment variables.
74 * Usefull to define some easy to use boot commands.
76 #define CFG_EXTRA_ENV_SETTINGS \
78 "basicargs=console=ttyS0,115200\0" \
82 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
83 * leaving the correct space for initial global data structure above that
84 * address while providing maximum stack area below.
86 #define CFG_SYS_INIT_RAM_SIZE 0x1000
87 #define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
91 #define CFG_SYS_NAND_U_BOOT_SIZE SZ_512K
92 #define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
93 #define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
95 #define CFG_SYS_NAND_ECCSIZE 256
96 #define CFG_SYS_NAND_ECCBYTES 3
97 #define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
98 48, 49, 50, 51, 52, 53, 54, 55, \
99 56, 57, 58, 59, 60, 61, 62, 63, }
101 #define CFG_SYS_MASTER_CLOCK (198656000/2)
102 #define AT91_PLL_LOCK_TIMEOUT 1000000
103 #define CFG_SYS_AT91_PLLA 0x2060bf09
104 #define CFG_SYS_MCKR 0x100
105 #define CFG_SYS_MCKR_CSS (0x02 | CFG_SYS_MCKR)
106 #define CFG_SYS_AT91_PLLB 0x10483f0e
108 #endif /* __CONFIG_H */