1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
8 * Achim Ehrlich <aehrlich@taskit.de>
9 * taskit GmbH <www.taskit.de>
12 * Markus Hubig <mhubig@imko.de>
13 * IMKO GmbH <www.imko.de>
16 * Heiko Schocher <hs@denx.de>
17 * DENX Software Engineering GmbH
19 * Configuation settings for the smartweb.
26 * SoC must be defined first, before hardware.h is included.
27 * In this case SoC is defined in boards.cfg.
29 #include <asm/hardware.h>
30 #include <linux/sizes.h>
33 * Warning: changing CONFIG_SYS_TEXT_BASE requires adapting the initial boot
34 * program. Since the linker has to swallow that define, we must use a pure
38 /* ARM asynchronous clock */
39 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
40 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */
44 /* We set the max number of command args high to avoid HUSH bugs. */
45 #define CONFIG_SYS_MAXARGS 32
47 /* setting board specific options */
48 #define CONFIG_SYS_AUTOLOAD "yes"
51 #define CONFIG_RED_LED AT91_PIN_PA9
52 #define CONFIG_GREEN_LED AT91_PIN_PA6
55 * SDRAM: 1 bank, 64 MB, base address 0x20000000
56 * Already initialized before u-boot gets started.
58 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
59 #define CONFIG_SYS_SDRAM_SIZE (64 * SZ_1M)
62 * Perform a SDRAM Memtest from the start of SDRAM
63 * till the beginning of the U-Boot position in RAM.
66 /* NAND flash settings */
67 #define CONFIG_SYS_MAX_NAND_DEVICE 1
68 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
69 #define CONFIG_SYS_NAND_DBW_8
70 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
71 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
72 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
73 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
76 #define CONFIG_USART_BASE ATMEL_BASE_DBGU
77 #define CONFIG_USART_ID ATMEL_ID_SYS
79 #if !defined(CONFIG_SPL_BUILD)
80 /* USB configuration */
81 #define CONFIG_USB_ATMEL
82 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
83 #define CONFIG_USB_OHCI_NEW
84 #define CONFIG_SYS_USB_OHCI_CPU_INIT
85 #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
86 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
87 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
91 #define CONFIG_USB_GADGET_AT91
93 /* DFU class support */
94 #define DFU_MANIFEST_POLL_TIMEOUT 25000
97 /* General Boot Parameter */
98 #define CONFIG_SYS_CBSIZE 512
101 * The NAND Flash partitions:
103 #define CONFIG_ENV_RANGE (SZ_512K)
106 * Predefined environment variables.
107 * Usefull to define some easy to use boot commands.
109 #define CONFIG_EXTRA_ENV_SETTINGS \
111 "basicargs=console=ttyS0,115200\0" \
113 "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0"
115 #ifdef CONFIG_SPL_BUILD
116 #define CONFIG_SYS_INIT_SP_ADDR 0x301000
119 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
120 * leaving the correct space for initial global data structure above that
121 * address while providing maximum stack area below.
123 #define CONFIG_SYS_INIT_SP_ADDR \
124 (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
127 /* Defines for SPL */
128 #define CONFIG_SPL_MAX_SIZE (SZ_4K)
130 #define CONFIG_SPL_BSS_START_ADDR CONFIG_SYS_SDRAM_BASE
131 #define CONFIG_SPL_BSS_MAX_SIZE (SZ_16K)
132 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
133 CONFIG_SPL_BSS_MAX_SIZE)
134 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
136 #define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
137 #define CONFIG_SPL_NAND_RAW_ONLY
138 #define CONFIG_SPL_NAND_SOFTECC
139 #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
140 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
141 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
143 #define CONFIG_SYS_NAND_SIZE (SZ_256M)
144 #define CONFIG_SYS_NAND_ECCSIZE 256
145 #define CONFIG_SYS_NAND_ECCBYTES 3
146 #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
147 48, 49, 50, 51, 52, 53, 54, 55, \
148 56, 57, 58, 59, 60, 61, 62, 63, }
150 #define CONFIG_SYS_MASTER_CLOCK (198656000/2)
151 #define AT91_PLL_LOCK_TIMEOUT 1000000
152 #define CONFIG_SYS_AT91_PLLA 0x2060bf09
153 #define CONFIG_SYS_MCKR 0x100
154 #define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
155 #define CONFIG_SYS_AT91_PLLB 0x10483f0e
157 #define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
158 #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
160 #endif /* __CONFIG_H */