1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
8 * Achim Ehrlich <aehrlich@taskit.de>
9 * taskit GmbH <www.taskit.de>
12 * Markus Hubig <mhubig@imko.de>
13 * IMKO GmbH <www.imko.de>
16 * Heiko Schocher <hs@denx.de>
17 * DENX Software Engineering GmbH
19 * Configuation settings for the smartweb.
26 * SoC must be defined first, before hardware.h is included.
27 * In this case SoC is defined in boards.cfg.
29 #include <asm/hardware.h>
30 #include <linux/sizes.h>
33 * Warning: changing CONFIG_SYS_TEXT_BASE requires adapting the initial boot
34 * program. Since the linker has to swallow that define, we must use a pure
38 /* ARM asynchronous clock */
39 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
40 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */
43 #define CONFIG_CMDLINE_TAG /* pass commandline to Kernel */
44 #define CONFIG_SETUP_MEMORY_TAGS /* pass memory defs to kernel */
45 #define CONFIG_INITRD_TAG /* pass initrd param to kernel */
47 /* We set the max number of command args high to avoid HUSH bugs. */
48 #define CONFIG_SYS_MAXARGS 32
50 /* setting board specific options */
51 #define CONFIG_MACH_TYPE MACH_TYPE_SMARTWEB
52 #define CONFIG_SYS_AUTOLOAD "yes"
53 #define CONFIG_RESET_TO_RETRY
56 #define CONFIG_RED_LED AT91_PIN_PA9
57 #define CONFIG_GREEN_LED AT91_PIN_PA6
60 * SDRAM: 1 bank, 64 MB, base address 0x20000000
61 * Already initialized before u-boot gets started.
63 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
64 #define CONFIG_SYS_SDRAM_SIZE (64 * SZ_1M)
67 * Perform a SDRAM Memtest from the start of SDRAM
68 * till the beginning of the U-Boot position in RAM.
71 /* NAND flash settings */
72 #define CONFIG_SYS_MAX_NAND_DEVICE 1
73 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
74 #define CONFIG_SYS_NAND_DBW_8
75 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
76 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
77 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
78 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
80 /* general purpose I/O */
81 #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
82 #define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
85 #define CONFIG_USART_BASE ATMEL_BASE_DBGU
86 #define CONFIG_USART_ID ATMEL_ID_SYS
89 * Ethernet configuration
93 #define CONFIG_RMII /* use reduced MII inteface */
94 #define CONFIG_NET_RETRY_COUNT 20 /* # of DHCP/BOOTP retries */
95 #define CONFIG_AT91_WANTS_COMMON_PHY
97 /* BOOTP and DHCP options */
98 #define CONFIG_BOOTP_BOOTFILESIZE
99 #define NFSBOOTCOMMAND \
100 "setenv autoload yes; setenv autoboot yes; " \
101 "setenv bootargs ${basicargs} ${mtdparts} " \
102 "root=/dev/nfs ip=dhcp nfsroot=${serverip}:/srv/nfs/rootfs; " \
105 #if !defined(CONFIG_SPL_BUILD)
106 /* USB configuration */
107 #define CONFIG_USB_ATMEL
108 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
109 #define CONFIG_USB_OHCI_NEW
110 #define CONFIG_SYS_USB_OHCI_CPU_INIT
111 #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
112 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
113 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
115 /* USB DFU support */
117 #define CONFIG_USB_GADGET_AT91
119 /* DFU class support */
120 #define DFU_MANIFEST_POLL_TIMEOUT 25000
123 /* General Boot Parameter */
124 #define CONFIG_BOOTCOMMAND "run flashboot"
125 #define CONFIG_SYS_CBSIZE 512
128 * The NAND Flash partitions:
130 #define CONFIG_ENV_RANGE (SZ_512K)
133 * Predefined environment variables.
134 * Usefull to define some easy to use boot commands.
136 #define CONFIG_EXTRA_ENV_SETTINGS \
138 "basicargs=console=ttyS0,115200\0" \
140 "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0"
142 #ifdef CONFIG_SPL_BUILD
143 #define CONFIG_SYS_INIT_SP_ADDR 0x301000
144 #define CONFIG_SPL_STACK_R
145 #define CONFIG_SPL_STACK_R_ADDR CONFIG_SYS_TEXT_BASE
148 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
149 * leaving the correct space for initial global data structure above that
150 * address while providing maximum stack area below.
152 #define CONFIG_SYS_INIT_SP_ADDR \
153 (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
156 /* Defines for SPL */
157 #define CONFIG_SPL_MAX_SIZE (SZ_4K)
159 #define CONFIG_SPL_BSS_START_ADDR CONFIG_SYS_SDRAM_BASE
160 #define CONFIG_SPL_BSS_MAX_SIZE (SZ_16K)
161 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
162 CONFIG_SPL_BSS_MAX_SIZE)
163 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
165 #define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
166 #define CONFIG_SYS_USE_NANDFLASH 1
167 #define CONFIG_SPL_NAND_RAW_ONLY
168 #define CONFIG_SPL_NAND_SOFTECC
169 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
170 #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
171 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
172 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
173 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
175 #define CONFIG_SYS_NAND_SIZE (SZ_256M)
176 #define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K
177 #define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K)
178 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
179 CONFIG_SYS_NAND_PAGE_SIZE)
180 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
181 #define CONFIG_SYS_NAND_ECCSIZE 256
182 #define CONFIG_SYS_NAND_ECCBYTES 3
183 #define CONFIG_SYS_NAND_OOBSIZE 64
184 #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
185 48, 49, 50, 51, 52, 53, 54, 55, \
186 56, 57, 58, 59, 60, 61, 62, 63, }
188 #define CONFIG_SPL_ATMEL_SIZE
189 #define CONFIG_SYS_MASTER_CLOCK (198656000/2)
190 #define AT91_PLL_LOCK_TIMEOUT 1000000
191 #define CONFIG_SYS_AT91_PLLA 0x2060bf09
192 #define CONFIG_SYS_MCKR 0x100
193 #define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
194 #define CONFIG_SYS_AT91_PLLB 0x10483f0e
196 #define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
197 #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
199 #endif /* __CONFIG_H */