1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Renesas SH7763RDP board
5 * Copyright (C) 2008 Renesas Solutions Corp.
6 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
12 #define CONFIG_CPU_SH7763 1
13 #define __LITTLE_ENDIAN 1
15 #define CONFIG_ENV_OVERWRITE 1
17 #define CONFIG_DISPLAY_BOARDINFO
20 #define CONFIG_CONS_SCIF2 1
22 #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
23 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate
24 settings for this board */
27 #define CONFIG_SYS_SDRAM_BASE (0x8C000000)
28 #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
31 #define CONFIG_SYS_FLASH_BASE (0xA0000000)
32 #define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
33 #define CONFIG_SYS_MAX_FLASH_BANKS (1)
34 #define CONFIG_SYS_MAX_FLASH_SECT (520)
37 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
38 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
39 #define CONFIG_SYS_MONITOR_LEN (128 * 1024)
40 /* Size of DRAM reserved for malloc() use */
41 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
42 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
44 #undef CONFIG_SYS_FLASH_QUIET_TEST
45 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
46 /* Timeout for Flash erase operations (in ms) */
47 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
48 /* Timeout for Flash write operations (in ms) */
49 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
50 /* Timeout for Flash set sector lock bit operations (in ms) */
51 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
52 /* Timeout for Flash clear lock bit operations (in ms) */
53 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
54 /* Use hardware flash sectors protection instead of U-Boot software protection */
55 #undef CONFIG_SYS_DIRECT_FLASH_TFTP
56 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
59 #define CONFIG_SYS_CLK_FREQ 66666666
60 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
63 #define CONFIG_SH_ETHER_USE_PORT (1)
64 #define CONFIG_SH_ETHER_PHY_ADDR (0x01)
65 #define CONFIG_BITBANGMII_MULTI
66 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
68 #endif /* __SH7763RDP_H */