2 * Configuation settings for the Renesas SH7763RDP board
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
7 * SPDX-License-Identifier: GPL-2.0+
13 #define CONFIG_CPU_SH7763 1
14 #define CONFIG_SH7763RDP 1
15 #define __LITTLE_ENDIAN 1
18 * Command line configuration.
20 #define CONFIG_CMD_SDRAM
21 #define CONFIG_CMD_MII
22 #define CONFIG_CMD_PING
23 #define CONFIG_CMD_JFFS2
25 #define CONFIG_BOOTDELAY -1
26 #define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01"
27 #define CONFIG_ENV_OVERWRITE 1
29 #define CONFIG_VERSION_VARIABLE
30 #undef CONFIG_SHOW_BOOT_PROGRESS
33 #define CONFIG_SCIF_CONSOLE 1
34 #define CONFIG_BAUDRATE 115200
35 #define CONFIG_CONS_SCIF2 1
37 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000
38 #define CONFIG_SYS_LONGHELP /* undef to save memory */
39 #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
40 #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
41 #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
42 #define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments
44 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate
45 settings for this board */
48 #define CONFIG_SYS_SDRAM_BASE (0x8C000000)
49 #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
50 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
51 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
54 #define CONFIG_SYS_FLASH_BASE (0xA0000000)
55 #define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
56 #define CONFIG_SYS_MAX_FLASH_BANKS (1)
57 #define CONFIG_SYS_MAX_FLASH_SECT (520)
60 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
61 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
62 #define CONFIG_SYS_MONITOR_LEN (128 * 1024)
63 /* Size of DRAM reserved for malloc() use */
64 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
65 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
67 #define CONFIG_SYS_FLASH_CFI
68 #define CONFIG_FLASH_CFI_DRIVER
69 #undef CONFIG_SYS_FLASH_QUIET_TEST
70 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
71 /* Timeout for Flash erase operations (in ms) */
72 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
73 /* Timeout for Flash write operations (in ms) */
74 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
75 /* Timeout for Flash set sector lock bit operations (in ms) */
76 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
77 /* Timeout for Flash clear lock bit operations (in ms) */
78 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
79 /* Use hardware flash sectors protection instead of U-Boot software protection */
80 #undef CONFIG_SYS_FLASH_PROTECTION
81 #undef CONFIG_SYS_DIRECT_FLASH_TFTP
82 #define CONFIG_ENV_IS_IN_FLASH
83 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
84 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
85 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
86 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
87 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
88 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
89 #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
92 #define CONFIG_SYS_CLK_FREQ 66666666
93 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
94 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
95 #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
98 #define CONFIG_SH_ETHER 1
99 #define CONFIG_SH_ETHER_USE_PORT (1)
100 #define CONFIG_SH_ETHER_PHY_ADDR (0x01)
101 #define CONFIG_PHYLIB
102 #define CONFIG_BITBANGMII
103 #define CONFIG_BITBANGMII_MULTI
104 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
106 #endif /* __SH7763RDP_H */