1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the sh7757lcr board
5 * Copyright (C) 2011 Renesas Solutions Corp.
11 #define CONFIG_CPU_SH7757 1
12 #define CONFIG_SH7757LCR_DDR_ECC 1
14 #define CONFIG_DISPLAY_BOARDINFO
17 #define SH7757LCR_SDRAM_BASE (0x80000000)
18 #define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024)
19 #define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */
20 #define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024)
22 #define CONFIG_SYS_PBSIZE 256
23 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
26 #define CONFIG_CONS_SCIF2 1
28 #define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE)
29 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
31 #undef CONFIG_SYS_MEMTEST_SCRATCH
32 #undef CONFIG_SYS_LOADS_BAUD_CHANGE
34 #define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE)
35 #define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE)
36 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
37 (128 + 16) * 1024 * 1024)
39 #define CONFIG_SYS_MONITOR_BASE 0x00000000
40 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
41 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
42 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
45 #define CONFIG_SH_ETHER_USE_PORT 0
46 #define CONFIG_SH_ETHER_PHY_ADDR 1
47 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
48 #define CONFIG_BITBANGMII
49 #define CONFIG_BITBANGMII_MULTI
50 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
52 #define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000
53 #define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024)
54 #define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI
55 #define SH7757LCR_ETHERNET_MAC_SIZE 17
56 #define SH7757LCR_ETHERNET_NUM_CH 2
59 #define SH7757LCR_GIGA_ETHERNET_NUM_CH 2
62 #define CONFIG_SH_SPI_BASE 0xfe002000
65 #define CONFIG_SH_MMCIF_ADDR 0xffcb0000
66 #define CONFIG_SH_MMCIF_CLK 48000000
69 #define SH7757LCR_SDRAM_PHYS_TOP 0x40000000
70 #define SH7757LCR_GRA_OFFSET 0x1f000000
71 #define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000
72 #define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024)
73 #define SH7757LCR_PCIEBRG_ADDR 0x00090000
74 #define SH7757LCR_PCIEBRG_SIZE (96 * 1024)
77 #define CONFIG_ENV_OVERWRITE 1
78 #define CONFIG_EXTRA_ENV_SETTINGS \
79 "netboot=bootp; bootm\0"
82 #define CONFIG_SYS_CLK_FREQ 48000000
83 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
84 #endif /* __SH7757LCR_H */