1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the sh7752evb board
5 * Copyright (C) 2012 Renesas Solutions Corp.
11 #define CONFIG_CPU_SH7752 1
13 #define CONFIG_DISPLAY_BOARDINFO
14 #undef CONFIG_SHOW_BOOT_PROGRESS
17 #define SH7752EVB_SDRAM_BASE (0x40000000)
18 #define SH7752EVB_SDRAM_SIZE (512 * 1024 * 1024)
20 #define CONFIG_SYS_PBSIZE 256
21 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
24 #define CONFIG_CONS_SCIF2 1
26 #define CONFIG_SYS_MEMTEST_START (SH7752EVB_SDRAM_BASE)
27 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
29 #undef CONFIG_SYS_MEMTEST_SCRATCH
30 #undef CONFIG_SYS_LOADS_BAUD_CHANGE
32 #define CONFIG_SYS_SDRAM_BASE (SH7752EVB_SDRAM_BASE)
33 #define CONFIG_SYS_SDRAM_SIZE (SH7752EVB_SDRAM_SIZE)
34 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
37 #define CONFIG_SYS_MONITOR_BASE 0x00000000
38 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
39 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
40 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
43 #define CONFIG_SH_ETHER_USE_PORT 0
44 #define CONFIG_SH_ETHER_PHY_ADDR 18
45 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
46 #define CONFIG_SH_ETHER_USE_GETHER 1
47 #define CONFIG_BITBANGMII
48 #define CONFIG_BITBANGMII_MULTI
49 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
50 #define CONFIG_PHY_VITESSE
52 #define SH7752EVB_ETHERNET_MAC_BASE_SPI 0x00090000
53 #define SH7752EVB_SPI_SECTOR_SIZE (64 * 1024)
54 #define SH7752EVB_ETHERNET_MAC_BASE SH7752EVB_ETHERNET_MAC_BASE_SPI
55 #define SH7752EVB_ETHERNET_MAC_SIZE 17
56 #define SH7752EVB_ETHERNET_NUM_CH 2
59 #define CONFIG_SH_SPI_BASE 0xfe002000
62 #define CONFIG_SH_MMCIF_ADDR 0xffcb0000
63 #define CONFIG_SH_MMCIF_CLK 48000000
66 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
67 #define CONFIG_ENV_ADDR (0x00080000)
68 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
69 #define CONFIG_ENV_OVERWRITE 1
70 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
71 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
72 #define CONFIG_EXTRA_ENV_SETTINGS \
73 "netboot=bootp; bootm\0"
76 #define CONFIG_SYS_CLK_FREQ 48000000
77 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
78 #endif /* __SH7752EVB_H */