2 * (C) Copyright 2006-2008
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
6 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
7 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
9 * SPDX-License-Identifier: GPL-2.0+
13 * sequoia.h - configuration for Sequoia & Rainier boards
19 * High Level Configuration Options
21 /* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
22 #ifndef CONFIG_RAINIER
23 #define CONFIG_440EPX 1 /* Specific PPC440EPx */
24 #define CONFIG_HOSTNAME sequoia
26 #define CONFIG_440GRX 1 /* Specific PPC440GRx */
27 #define CONFIG_HOSTNAME rainier
29 #define CONFIG_440 1 /* ... PPC440 family */
31 #ifndef CONFIG_SYS_TEXT_BASE
32 #define CONFIG_SYS_TEXT_BASE 0xFFF80000
36 * Include common defines/options for all AMCC eval boards
38 #include "amcc-common.h"
40 /* Detect Sequoia PLL input clock automatically via CPLD bit */
41 #define CONFIG_SYS_CLK_FREQ ((in8(CONFIG_SYS_BCSR_BASE + 3) & 0x80) ? \
45 * Define this if you want support for video console with radeon 9200 pci card
46 * Also set CONFIG_SYS_TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case
52 * 44x dcache supported is working now on sequoia, but we don't enable
53 * it yet since it needs further testing
55 #define CONFIG_4xx_DCACHE /* enable dcache */
58 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
59 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
62 * Base addresses -- Note these are effective addresses where the actual
63 * resources get mapped (not physical addresses).
65 #define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0x0003
66 #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
67 #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
68 #define CONFIG_SYS_NAND_ADDR 0xd0000000 /* NAND Flash */
69 #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
70 #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
71 #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
72 #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
73 #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
74 #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
75 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
77 #define CONFIG_SYS_USB2D0_BASE 0xe0000100
78 #define CONFIG_SYS_USB_DEVICE 0xe0000000
79 #define CONFIG_SYS_USB_HOST 0xe0000400
80 #define CONFIG_SYS_BCSR_BASE 0xc0000000
83 * Initial RAM & stack pointer
85 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
86 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
87 #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
88 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
89 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
94 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
95 #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
100 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
101 #define CONFIG_ENV_IS_IN_NAND /* use NAND for environ vars */
102 #define CONFIG_ENV_IS_EMBEDDED /* use embedded environment */
103 #elif defined(CONFIG_SYS_RAMBOOT)
104 #define CONFIG_ENV_IS_NOWHERE /* Store env in memory only */
105 #define CONFIG_ENV_SIZE (8 << 10)
107 * In RAM-booting version, we have no environment storage. So we need to
108 * provide at least preliminary MAC addresses for the 4xx EMAC driver to
109 * register the interfaces. Those two addresses are generated via the
110 * tools/gen_eth_addr tool and should only be used in a closed laboratory
113 #define CONFIG_ETHADDR 4a:56:49:22:3e:43
114 #define CONFIG_ETH1ADDR 02:93:53:d5:06:98
116 #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environ vars */
119 #if defined(CONFIG_CMD_FLASH)
123 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
124 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
126 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
128 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
129 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
131 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
132 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
134 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
135 #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
137 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
138 #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
140 #ifdef CONFIG_ENV_IS_IN_FLASH
141 #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
142 #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
143 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
145 /* Address and size of Redundant Environment Sector */
146 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
147 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
149 #endif /* CONFIG_CMD_FLASH */
152 * IPL (Initial Program Loader, integrated inside CPU)
153 * Will load first 4k from NAND (SPL) into cache and execute it from there.
155 * SPL (Secondary Program Loader)
156 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
157 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
158 * controller and the NAND controller so that the special U-Boot image can be
159 * loaded from NAND to SDRAM.
162 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
163 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
165 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
166 * set up. While still running from cache, I experienced problems accessing
167 * the NAND controller. sr - 2006-08-25
169 #define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
170 #define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
171 #define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */
172 #define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
173 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from */
175 #define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
178 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
180 #define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
181 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
184 * Now the NAND chip has to be defined (no autodetection used!)
186 #define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
187 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
188 #define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
189 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
190 #undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
192 #define CONFIG_SYS_NAND_ECCSIZE 256
193 #define CONFIG_SYS_NAND_ECCBYTES 3
194 #define CONFIG_SYS_NAND_OOBSIZE 16
195 #define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
197 #ifdef CONFIG_ENV_IS_IN_NAND
199 * For NAND booting the environment is embedded in the U-Boot image. Please take
200 * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
202 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
203 #define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
204 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
210 #define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
211 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
212 !defined(CONFIG_SYS_RAMBOOT)
213 #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
215 #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
216 /* 440EPx errata CHIP 11 */
221 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
223 #define CONFIG_SYS_I2C_MULTI_EEPROMS
224 #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
225 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
226 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
227 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
229 /* I2C bootstrap EEPROM */
230 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
231 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
232 #define CONFIG_4xx_CONFIG_BLOCKSIZE 16
234 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
235 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
236 #define CONFIG_DTT_AD7414 1 /* use AD7414 */
237 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
238 #define CONFIG_SYS_DTT_MAX_TEMP 70
239 #define CONFIG_SYS_DTT_LOW_TEMP -30
240 #define CONFIG_SYS_DTT_HYSTERESIS 3
243 * Default environment variables
245 #define CONFIG_EXTRA_ENV_SETTINGS \
246 CONFIG_AMCC_DEF_ENV \
247 CONFIG_AMCC_DEF_ENV_POWERPC \
248 CONFIG_AMCC_DEF_ENV_PPC_OLD \
249 CONFIG_AMCC_DEF_ENV_NOR_UPD \
250 CONFIG_AMCC_DEF_ENV_NAND_UPD \
251 "kernel_addr=FC000000\0" \
252 "ramdisk_addr=FC180000\0" \
255 #define CONFIG_M88E1111_PHY 1
256 #define CONFIG_IBM_EMAC4_V4 1
257 #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
259 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
260 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
262 #define CONFIG_HAS_ETH0
263 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
264 #define CONFIG_PHY1_ADDR 1
269 #undef CONFIG_USB_EHCI /* OHCI by default */
271 #ifdef CONFIG_USB_EHCI
272 #define CONFIG_USB_EHCI_PPC4XX
273 #define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
274 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
275 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
276 #define CONFIG_EHCI_DESC_BIG_ENDIAN
277 #else /* CONFIG_USB_EHCI */
278 #define CONFIG_USB_OHCI_NEW
279 #define CONFIG_SYS_OHCI_BE_CONTROLLER
281 #undef CONFIG_SYS_USB_OHCI_BOARD_INIT
282 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
283 #define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
284 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
285 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
288 #define CONFIG_USB_STORAGE
289 /* Comment this out to enable USB 1.1 device */
290 #define USB_2_0_DEVICE
292 #endif /* CONFIG_440EPX */
295 #define CONFIG_MAC_PARTITION
296 #define CONFIG_DOS_PARTITION
297 #define CONFIG_ISO_PARTITION
300 * Commands additional to the ones defined in amcc-common.h
302 #define CONFIG_CMD_CHIP_CONFIG
303 #define CONFIG_CMD_DTT
304 #define CONFIG_CMD_FAT
305 #define CONFIG_CMD_NAND
306 #define CONFIG_CMD_PCI
307 #define CONFIG_CMD_SDRAM
310 #define CONFIG_CMD_USB
313 #ifndef CONFIG_RAINIER
314 #define CONFIG_SYS_POST_FPU_ON CONFIG_SYS_POST_FPU
316 #define CONFIG_SYS_POST_FPU_ON 0
320 * Don't run the memory POST on the NAND-booting version. It will
321 * overwrite part of the U-Boot image which is already loaded from NAND
324 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
325 #define CONFIG_SYS_POST_MEMORY_ON 0
327 #define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
331 #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
332 CONFIG_SYS_POST_CPU | \
333 CONFIG_SYS_POST_ETHER | \
334 CONFIG_SYS_POST_FPU_ON | \
335 CONFIG_SYS_POST_I2C | \
336 CONFIG_SYS_POST_MEMORY_ON | \
337 CONFIG_SYS_POST_SPR | \
338 CONFIG_SYS_POST_UART)
340 #define CONFIG_LOGBUFFER
341 #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
343 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
345 #define CONFIG_SUPPORT_VFAT
351 #define CONFIG_PCI /* include pci support */
352 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
353 #define CONFIG_PCI_PNP /* do pci plug-and-play */
354 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
355 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
356 #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
357 /* CONFIG_SYS_PCI_MEMBASE */
358 /* Board-specific PCI */
359 #define CONFIG_SYS_PCI_TARGET_INIT
360 #define CONFIG_SYS_PCI_MASTER_INIT
361 #define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
363 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
364 #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
367 * External Bus Controller (EBC) Setup
371 * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
373 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
374 !defined(CONFIG_SYS_RAMBOOT)
375 #define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
376 /* Memory Bank 0 (NOR-FLASH) initialization */
377 #define CONFIG_SYS_EBC_PB0AP 0x03017200
378 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
380 /* Memory Bank 3 (NAND-FLASH) initialization */
381 #define CONFIG_SYS_EBC_PB3AP 0x018003c0
382 #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
384 #define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
385 /* Memory Bank 3 (NOR-FLASH) initialization */
386 #define CONFIG_SYS_EBC_PB3AP 0x03017200
387 #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FLASH_BASE | 0xda000)
389 /* Memory Bank 0 (NAND-FLASH) initialization */
390 #define CONFIG_SYS_EBC_PB0AP 0x018003c0
391 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
394 /* Memory Bank 2 (CPLD) initialization */
395 #define CONFIG_SYS_EBC_PB2AP 0x24814580
396 #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_BCSR_BASE | 0x38000)
398 #define CONFIG_SYS_BCSR5_PCI66EN 0x80
403 #define CONFIG_SYS_MAX_NAND_DEVICE 1
404 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
405 #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
408 * PPC440 GPIO Configuration
410 /* test-only: take GPIO init from pcs440ep ???? in config file */
411 #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
414 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
415 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
416 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
417 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
418 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
419 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
420 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
421 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
422 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
423 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
424 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
425 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
426 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
427 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
428 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14 */ \
429 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
430 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \
431 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \
432 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \
433 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \
434 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
435 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
436 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
437 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
438 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \
439 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \
440 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
441 {GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
442 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28 USB2D_TXVALID */ \
443 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
444 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
445 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
449 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
450 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
451 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_8PIN_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
452 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
453 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_CTS_N EBC_DATA(0) UART3_SIN*/ \
454 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
455 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_8PIN_DTR_N UART1_SOUT */ \
456 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_8PIN_RI_N UART1_SIN */ \
457 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
458 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
459 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
460 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
461 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
462 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
463 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
464 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
465 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
466 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
467 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
468 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
469 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
470 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
471 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
472 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
473 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
474 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
475 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
476 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
477 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
478 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
479 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
480 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
485 #define CONFIG_BIOSEMU /* x86 bios emulator for vga bios */
486 #define CONFIG_ATI_RADEON_FB /* use radeon framebuffer driver */
487 #define VIDEO_IO_OFFSET 0xe8000000
488 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
489 #define CONFIG_VIDEO_SW_CURSOR
490 #define CONFIG_VIDEO_LOGO
491 #define CONFIG_CFB_CONSOLE
492 #define CONFIG_SPLASH_SCREEN
493 #define CONFIG_VGA_AS_SINGLE_DEVICE
494 #define CONFIG_CMD_BMP
497 #endif /* __CONFIG_H */