1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2007 Wind River Systems <www.windriver.com>
4 * Copyright 2007 Embedded Specialties, Inc.
5 * Joe Hamman <joe.hamman@embeddedspecialties.com>
7 * Copyright 2006 Freescale Semiconductor.
9 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
13 * SBC8641D board configuration file
15 * Make sure you change the MAC address and other network params first,
16 * search for CONFIG_SERVERIP, etc in this file.
22 /* High Level Configuration Options */
23 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
26 #define CONFIG_SYS_DIAG_ADDR 0xff800000
29 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100
32 * virtual address to be used for temporary mappings. There
33 * should be 128k free at this VA.
35 #define CONFIG_SYS_SCRATCH_VA 0xe8000000
37 #define CONFIG_SYS_SRIO
38 #define CONFIG_SRIO1 /* SRIO port 1 */
40 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
41 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
42 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
43 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
45 #define CONFIG_ENV_OVERWRITE
47 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
49 #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/
50 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
51 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
52 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
53 #define CACHE_LINE_INTERLEAVING 0x20000000
54 #define PAGE_INTERLEAVING 0x21000000
55 #define BANK_INTERLEAVING 0x22000000
56 #define SUPER_BANK_INTERLEAVING 0x23000000
58 #define CONFIG_ALTIVEC 1
61 * L2CR setup -- make sure this is right for your board!
65 #define L2_ENABLE (L2CR_L2E)
67 #ifndef CONFIG_SYS_CLK_FREQ
68 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
71 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
74 * Base addresses -- Note these are effective addresses where the
75 * actual resources get mapped (not physical addresses)
77 #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
78 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
80 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
81 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
82 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
87 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
88 #define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */
89 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
90 #define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2
91 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
92 #define CONFIG_VERY_BIG_RAM
94 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
95 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
97 #if defined(CONFIG_SPD_EEPROM)
99 * Determine DDR configuration from I2C interface.
101 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */
102 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */
103 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */
104 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */
108 * Manually set up DDR1 & DDR2 parameters
111 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
113 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
114 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
115 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000
116 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000
117 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
118 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
119 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
120 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
121 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
122 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
123 #define CONFIG_SYS_DDR_TIMING_1 0x38377322
124 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7
125 #define CONFIG_SYS_DDR_CFG_1A 0x43008008
126 #define CONFIG_SYS_DDR_CFG_2 0x24401000
127 #define CONFIG_SYS_DDR_MODE_1 0x23c00542
128 #define CONFIG_SYS_DDR_MODE_2 0x00000000
129 #define CONFIG_SYS_DDR_MODE_CTL 0x00000000
130 #define CONFIG_SYS_DDR_INTERVAL 0x05080100
131 #define CONFIG_SYS_DDR_DATA_INIT 0x00000000
132 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
133 #define CONFIG_SYS_DDR_CFG_1B 0xC3008008
135 #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F
136 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
137 #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000
138 #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000
139 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102
140 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000
141 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
142 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
143 #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000
144 #define CONFIG_SYS_DDR2_TIMING_0 0x00220802
145 #define CONFIG_SYS_DDR2_TIMING_1 0x38377322
146 #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7
147 #define CONFIG_SYS_DDR2_CFG_1A 0x43008008
148 #define CONFIG_SYS_DDR2_CFG_2 0x24401000
149 #define CONFIG_SYS_DDR2_MODE_1 0x23c00542
150 #define CONFIG_SYS_DDR2_MODE_2 0x00000000
151 #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000
152 #define CONFIG_SYS_DDR2_INTERVAL 0x05080100
153 #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000
154 #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000
155 #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008
159 /* #define CONFIG_ID_EEPROM 1
160 #define ID_EEPROM_ADDR 0x57 */
163 * The SBC8641D contains 16MB flash space at ff000000.
165 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
168 #define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */
169 #define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */
172 #define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */
173 #define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */
175 /* EPLD - User switches, board id, LEDs */
176 #define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */
177 #define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */
179 /* Local bus SDRAM 128MB */
180 #define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */
181 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */
182 #define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */
183 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */
185 /* Disk on Chip (DOC) 128MB */
186 #define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */
187 #define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */
190 #define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */
191 #define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
193 /* Control logic & misc peripherals */
194 #define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */
195 #define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
197 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
198 #define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */
200 #undef CONFIG_SYS_FLASH_CHECKSUM
201 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
202 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
203 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
204 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
206 #define CONFIG_SYS_WRITE_SWAPPED_DATA
207 #define CONFIG_SYS_FLASH_EMPTY_INFO
209 #define CONFIG_SYS_INIT_RAM_LOCK 1
210 #ifndef CONFIG_SYS_INIT_RAM_LOCK
211 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
213 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
215 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
217 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
218 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
220 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
221 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
224 #define CONFIG_SYS_NS16550_SERIAL
225 #define CONFIG_SYS_NS16550_REG_SIZE 1
226 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
228 #define CONFIG_SYS_BAUDRATE_TABLE \
229 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
231 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
232 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
237 #define CONFIG_SYS_I2C
238 #define CONFIG_SYS_I2C_FSL
239 #define CONFIG_SYS_FSL_I2C_SPEED 400000
240 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
241 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
242 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
247 #define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */
248 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE
249 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
253 * Addresses are mapped 1-1.
255 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
256 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
257 #define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS
258 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
259 #define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000
260 #define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS
261 #define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS
262 #define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */
264 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
265 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
266 #define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS
267 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
268 #define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000
269 #define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS
270 #define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS
271 #define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */
273 #if defined(CONFIG_PCI)
275 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
279 #if !defined(CONFIG_PCI_PNP)
280 #define PCI_ENET0_IOADDR 0xe0000000
281 #define PCI_ENET0_MEMADDR 0xe0000000
282 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
285 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
287 #ifdef CONFIG_SCSI_AHCI
288 #define CONFIG_SATA_ULI5288
289 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
290 #define CONFIG_SYS_SCSI_MAX_LUN 1
291 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
294 #endif /* CONFIG_PCI */
296 #if defined(CONFIG_TSEC_ENET)
297 #define CONFIG_TSEC1 1
298 #define CONFIG_TSEC1_NAME "eTSEC1"
299 #define CONFIG_TSEC2 1
300 #define CONFIG_TSEC2_NAME "eTSEC2"
301 #define CONFIG_TSEC3 1
302 #define CONFIG_TSEC3_NAME "eTSEC3"
303 #define CONFIG_TSEC4 1
304 #define CONFIG_TSEC4_NAME "eTSEC4"
306 #define TSEC1_PHY_ADDR 0x1F
307 #define TSEC2_PHY_ADDR 0x00
308 #define TSEC3_PHY_ADDR 0x01
309 #define TSEC4_PHY_ADDR 0x02
310 #define TSEC1_PHYIDX 0
311 #define TSEC2_PHYIDX 0
312 #define TSEC3_PHYIDX 0
313 #define TSEC4_PHYIDX 0
314 #define TSEC1_FLAGS TSEC_GIGABIT
315 #define TSEC2_FLAGS TSEC_GIGABIT
316 #define TSEC3_FLAGS TSEC_GIGABIT
317 #define TSEC4_FLAGS TSEC_GIGABIT
319 #define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */
321 #define CONFIG_ETHPRIME "eTSEC1"
323 #endif /* CONFIG_TSEC_ENET */
326 * BAT0 2G Cacheable, non-guarded
329 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
330 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
331 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
332 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
335 * BAT1 1G Cache-inhibited, guarded
336 * 0x8000_0000 512M PCI-Express 1 Memory
337 * 0xa000_0000 512M PCI-Express 2 Memory
338 * Changed it for operating from 0xd0000000
340 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
341 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
342 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
343 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
344 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
347 * BAT2 512M Cache-inhibited, guarded
348 * 0xc000_0000 512M RapidIO Memory
350 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
351 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
352 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
353 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
354 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
357 * BAT3 4M Cache-inhibited, guarded
358 * 0xf800_0000 4M CCSR
360 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
361 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
362 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
363 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
364 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
366 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
367 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
368 | BATL_PP_RW | BATL_CACHEINHIBIT \
369 | BATL_GUARDEDSTORAGE)
370 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
371 | BATU_BL_1M | BATU_VS | BATU_VP)
372 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
373 | BATL_PP_RW | BATL_CACHEINHIBIT)
374 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
378 * BAT4 32M Cache-inhibited, guarded
379 * 0xe200_0000 16M PCI-Express 1 I/O
380 * 0xe300_0000 16M PCI-Express 2 I/0
381 * Note that this is at 0xe0000000
383 #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \
384 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
385 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
386 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
387 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
390 * BAT5 128K Cacheable, non-guarded
391 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
393 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
394 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
395 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
396 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
399 * BAT6 32M Cache-inhibited, guarded
400 * 0xfe00_0000 32M FLASH
402 #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
403 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
404 #define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
405 #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
406 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
408 /* Map the last 1M of flash where we're running from reset */
409 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
410 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
411 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
412 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
414 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
416 #define CONFIG_SYS_DBAT7L 0x00000000
417 #define CONFIG_SYS_DBAT7U 0x00000000
418 #define CONFIG_SYS_IBAT7L 0x00000000
419 #define CONFIG_SYS_IBAT7U 0x00000000
425 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
426 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
428 #undef CONFIG_WATCHDOG /* watchdog disabled */
431 * Miscellaneous configurable options
433 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
436 * For booting Linux, the board info and command line data
437 * have to be in the first 8 MB of memory, since this is
438 * the maximum mapped by the Linux kernel during initialization.
440 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
442 /* Cache Configuration */
443 #define CONFIG_SYS_DCACHE_SIZE 32768
444 #define CONFIG_SYS_CACHELINE_SIZE 32
445 #if defined(CONFIG_CMD_KGDB)
446 #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
449 #if defined(CONFIG_CMD_KGDB)
450 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
454 * Environment Configuration
457 #define CONFIG_HAS_ETH0 1
458 #define CONFIG_HAS_ETH1 1
459 #define CONFIG_HAS_ETH2 1
460 #define CONFIG_HAS_ETH3 1
462 #define CONFIG_IPADDR 192.168.0.50
464 #define CONFIG_HOSTNAME "sbc8641d"
465 #define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx"
466 #define CONFIG_BOOTFILE "uImage"
468 #define CONFIG_SERVERIP 192.168.0.2
469 #define CONFIG_GATEWAYIP 192.168.0.1
470 #define CONFIG_NETMASK 255.255.255.0
472 /* default location for tftp and bootm */
473 #define CONFIG_LOADADDR 1000000
475 #define CONFIG_EXTRA_ENV_SETTINGS \
477 "consoledev=ttyS0\0" \
478 "ramdiskaddr=2000000\0" \
479 "ramdiskfile=uRamdisk\0" \
481 "dtbfile=sbc8641d.dtb\0" \
482 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
483 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
486 #define CONFIG_NFSBOOTCOMMAND \
487 "setenv bootargs root=/dev/nfs rw " \
488 "nfsroot=$serverip:$rootpath " \
489 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
490 "console=$consoledev,$baudrate $othbootargs;" \
491 "tftp $loadaddr $bootfile;" \
492 "tftp $dtbaddr $dtbfile;" \
493 "bootm $loadaddr - $dtbaddr"
495 #define CONFIG_RAMBOOTCOMMAND \
496 "setenv bootargs root=/dev/ram rw " \
497 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
498 "console=$consoledev,$baudrate $othbootargs;" \
499 "tftp $ramdiskaddr $ramdiskfile;" \
500 "tftp $loadaddr $bootfile;" \
501 "tftp $dtbaddr $dtbfile;" \
502 "bootm $loadaddr $ramdiskaddr $dtbaddr"
504 #define CONFIG_FLASHBOOTCOMMAND \
505 "setenv bootargs root=/dev/ram rw " \
506 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
507 "console=$consoledev,$baudrate $othbootargs;" \
508 "bootm ffd00000 ffb00000 ffa00000"
510 #define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND
512 #endif /* __CONFIG_H */