2 * Copyright 2007 Wind River Systems <www.windriver.com>
3 * Copyright 2007 Embedded Specialties, Inc.
4 * Joe Hamman <joe.hamman@embeddedspecialties.com>
6 * Copyright 2006 Freescale Semiconductor.
8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
10 * SPDX-License-Identifier: GPL-2.0+
14 * SBC8641D board configuration file
16 * Make sure you change the MAC address and other network params first,
17 * search for CONFIG_SERVERIP, etc in this file.
23 /* High Level Configuration Options */
24 #define CONFIG_SBC8641D 1 /* SBC8641D board specific */
25 #define CONFIG_MP 1 /* support multiple processors */
26 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
28 #define CONFIG_SYS_TEXT_BASE 0xfff00000
31 #define CONFIG_SYS_DIAG_ADDR 0xff800000
34 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100
37 * virtual address to be used for temporary mappings. There
38 * should be 128k free at this VA.
40 #define CONFIG_SYS_SCRATCH_VA 0xe8000000
42 #define CONFIG_SYS_SRIO
43 #define CONFIG_SRIO1 /* SRIO port 1 */
45 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
46 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
47 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
48 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
49 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
51 #define CONFIG_TSEC_ENET /* tsec ethernet support */
52 #define CONFIG_ENV_OVERWRITE
54 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
55 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
57 #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/
58 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
59 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
60 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
61 #define CONFIG_NUM_DDR_CONTROLLERS 2
62 #define CACHE_LINE_INTERLEAVING 0x20000000
63 #define PAGE_INTERLEAVING 0x21000000
64 #define BANK_INTERLEAVING 0x22000000
65 #define SUPER_BANK_INTERLEAVING 0x23000000
67 #define CONFIG_ALTIVEC 1
70 * L2CR setup -- make sure this is right for your board!
74 #define L2_ENABLE (L2CR_L2E)
76 #ifndef CONFIG_SYS_CLK_FREQ
77 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
80 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
82 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
83 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
84 #define CONFIG_SYS_MEMTEST_END 0x00400000
87 * Base addresses -- Note these are effective addresses where the
88 * actual resources get mapped (not physical addresses)
90 #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
91 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
93 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
94 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
95 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
100 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
101 #define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */
102 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
103 #define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2
104 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
105 #define CONFIG_VERY_BIG_RAM
107 #define CONFIG_NUM_DDR_CONTROLLERS 2
108 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
109 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
111 #if defined(CONFIG_SPD_EEPROM)
113 * Determine DDR configuration from I2C interface.
115 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */
116 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */
117 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */
118 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */
122 * Manually set up DDR1 & DDR2 parameters
125 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
127 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
128 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
129 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000
130 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000
131 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
132 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
133 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
134 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
135 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
136 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
137 #define CONFIG_SYS_DDR_TIMING_1 0x38377322
138 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7
139 #define CONFIG_SYS_DDR_CFG_1A 0x43008008
140 #define CONFIG_SYS_DDR_CFG_2 0x24401000
141 #define CONFIG_SYS_DDR_MODE_1 0x23c00542
142 #define CONFIG_SYS_DDR_MODE_2 0x00000000
143 #define CONFIG_SYS_DDR_MODE_CTL 0x00000000
144 #define CONFIG_SYS_DDR_INTERVAL 0x05080100
145 #define CONFIG_SYS_DDR_DATA_INIT 0x00000000
146 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
147 #define CONFIG_SYS_DDR_CFG_1B 0xC3008008
149 #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F
150 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
151 #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000
152 #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000
153 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102
154 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000
155 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
156 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
157 #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000
158 #define CONFIG_SYS_DDR2_TIMING_0 0x00220802
159 #define CONFIG_SYS_DDR2_TIMING_1 0x38377322
160 #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7
161 #define CONFIG_SYS_DDR2_CFG_1A 0x43008008
162 #define CONFIG_SYS_DDR2_CFG_2 0x24401000
163 #define CONFIG_SYS_DDR2_MODE_1 0x23c00542
164 #define CONFIG_SYS_DDR2_MODE_2 0x00000000
165 #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000
166 #define CONFIG_SYS_DDR2_INTERVAL 0x05080100
167 #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000
168 #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000
169 #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008
173 /* #define CONFIG_ID_EEPROM 1
174 #define ID_EEPROM_ADDR 0x57 */
177 * The SBC8641D contains 16MB flash space at ff000000.
179 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
182 #define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */
183 #define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */
186 #define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */
187 #define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */
189 /* EPLD - User switches, board id, LEDs */
190 #define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */
191 #define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */
193 /* Local bus SDRAM 128MB */
194 #define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */
195 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */
196 #define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */
197 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */
199 /* Disk on Chip (DOC) 128MB */
200 #define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */
201 #define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */
204 #define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */
205 #define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
207 /* Control logic & misc peripherals */
208 #define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */
209 #define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
211 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
212 #define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */
214 #undef CONFIG_SYS_FLASH_CHECKSUM
215 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
216 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
217 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
218 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
220 #define CONFIG_FLASH_CFI_DRIVER
221 #define CONFIG_SYS_FLASH_CFI
222 #define CONFIG_SYS_WRITE_SWAPPED_DATA
223 #define CONFIG_SYS_FLASH_EMPTY_INFO
224 #define CONFIG_SYS_FLASH_PROTECTION
226 #undef CONFIG_CLOCKS_IN_MHZ
228 #define CONFIG_SYS_INIT_RAM_LOCK 1
229 #ifndef CONFIG_SYS_INIT_RAM_LOCK
230 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
232 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
234 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
236 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
237 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
239 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
240 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
243 #define CONFIG_CONS_INDEX 1
244 #define CONFIG_SYS_NS16550_SERIAL
245 #define CONFIG_SYS_NS16550_REG_SIZE 1
246 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
248 #define CONFIG_SYS_BAUDRATE_TABLE \
249 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
251 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
252 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
257 #define CONFIG_SYS_I2C
258 #define CONFIG_SYS_I2C_FSL
259 #define CONFIG_SYS_FSL_I2C_SPEED 400000
260 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
261 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
262 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
267 #define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */
268 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE
269 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
273 * Addresses are mapped 1-1.
275 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
276 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
277 #define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS
278 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
279 #define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000
280 #define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS
281 #define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS
282 #define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */
284 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
285 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
286 #define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS
287 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
288 #define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000
289 #define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS
290 #define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS
291 #define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */
293 #if defined(CONFIG_PCI)
295 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
297 #undef CONFIG_EEPRO100
300 #if !defined(CONFIG_PCI_PNP)
301 #define PCI_ENET0_IOADDR 0xe0000000
302 #define PCI_ENET0_MEMADDR 0xe0000000
303 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
306 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
308 #define CONFIG_DOS_PARTITION
309 #undef CONFIG_SCSI_AHCI
311 #ifdef CONFIG_SCSI_AHCI
312 #define CONFIG_SATA_ULI5288
313 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
314 #define CONFIG_SYS_SCSI_MAX_LUN 1
315 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
316 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
319 #endif /* CONFIG_PCI */
321 #if defined(CONFIG_TSEC_ENET)
323 /* #define CONFIG_MII 1 */ /* MII PHY management */
325 #define CONFIG_TSEC1 1
326 #define CONFIG_TSEC1_NAME "eTSEC1"
327 #define CONFIG_TSEC2 1
328 #define CONFIG_TSEC2_NAME "eTSEC2"
329 #define CONFIG_TSEC3 1
330 #define CONFIG_TSEC3_NAME "eTSEC3"
331 #define CONFIG_TSEC4 1
332 #define CONFIG_TSEC4_NAME "eTSEC4"
334 #define TSEC1_PHY_ADDR 0x1F
335 #define TSEC2_PHY_ADDR 0x00
336 #define TSEC3_PHY_ADDR 0x01
337 #define TSEC4_PHY_ADDR 0x02
338 #define TSEC1_PHYIDX 0
339 #define TSEC2_PHYIDX 0
340 #define TSEC3_PHYIDX 0
341 #define TSEC4_PHYIDX 0
342 #define TSEC1_FLAGS TSEC_GIGABIT
343 #define TSEC2_FLAGS TSEC_GIGABIT
344 #define TSEC3_FLAGS TSEC_GIGABIT
345 #define TSEC4_FLAGS TSEC_GIGABIT
347 #define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */
349 #define CONFIG_ETHPRIME "eTSEC1"
351 #endif /* CONFIG_TSEC_ENET */
354 * BAT0 2G Cacheable, non-guarded
357 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
358 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
359 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
360 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
363 * BAT1 1G Cache-inhibited, guarded
364 * 0x8000_0000 512M PCI-Express 1 Memory
365 * 0xa000_0000 512M PCI-Express 2 Memory
366 * Changed it for operating from 0xd0000000
368 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
369 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
370 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
371 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
372 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
375 * BAT2 512M Cache-inhibited, guarded
376 * 0xc000_0000 512M RapidIO Memory
378 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
379 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
380 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
381 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
382 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
385 * BAT3 4M Cache-inhibited, guarded
386 * 0xf800_0000 4M CCSR
388 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
389 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
390 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
391 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
392 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
394 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
395 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
396 | BATL_PP_RW | BATL_CACHEINHIBIT \
397 | BATL_GUARDEDSTORAGE)
398 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
399 | BATU_BL_1M | BATU_VS | BATU_VP)
400 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
401 | BATL_PP_RW | BATL_CACHEINHIBIT)
402 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
406 * BAT4 32M Cache-inhibited, guarded
407 * 0xe200_0000 16M PCI-Express 1 I/O
408 * 0xe300_0000 16M PCI-Express 2 I/0
409 * Note that this is at 0xe0000000
411 #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \
412 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
413 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
414 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
415 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
418 * BAT5 128K Cacheable, non-guarded
419 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
421 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
422 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
423 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
424 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
427 * BAT6 32M Cache-inhibited, guarded
428 * 0xfe00_0000 32M FLASH
430 #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
431 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
432 #define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
433 #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
434 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
436 /* Map the last 1M of flash where we're running from reset */
437 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
438 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
439 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
440 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
442 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
444 #define CONFIG_SYS_DBAT7L 0x00000000
445 #define CONFIG_SYS_DBAT7U 0x00000000
446 #define CONFIG_SYS_IBAT7L 0x00000000
447 #define CONFIG_SYS_IBAT7U 0x00000000
452 #define CONFIG_ENV_IS_IN_FLASH 1
453 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
454 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k(one sector) for env */
455 #define CONFIG_ENV_SIZE 0x2000
457 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
458 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
460 #define CONFIG_CMD_REGINFO
462 #if defined(CONFIG_PCI)
463 #define CONFIG_CMD_PCI
466 #undef CONFIG_WATCHDOG /* watchdog disabled */
469 * Miscellaneous configurable options
471 #define CONFIG_SYS_LONGHELP /* undef to save memory */
472 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
473 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
475 #if defined(CONFIG_CMD_KGDB)
476 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
478 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
481 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
482 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
483 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
486 * For booting Linux, the board info and command line data
487 * have to be in the first 8 MB of memory, since this is
488 * the maximum mapped by the Linux kernel during initialization.
490 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
492 /* Cache Configuration */
493 #define CONFIG_SYS_DCACHE_SIZE 32768
494 #define CONFIG_SYS_CACHELINE_SIZE 32
495 #if defined(CONFIG_CMD_KGDB)
496 #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
499 #if defined(CONFIG_CMD_KGDB)
500 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
504 * Environment Configuration
507 #define CONFIG_HAS_ETH0 1
508 #define CONFIG_HAS_ETH1 1
509 #define CONFIG_HAS_ETH2 1
510 #define CONFIG_HAS_ETH3 1
512 #define CONFIG_IPADDR 192.168.0.50
514 #define CONFIG_HOSTNAME sbc8641d
515 #define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx"
516 #define CONFIG_BOOTFILE "uImage"
518 #define CONFIG_SERVERIP 192.168.0.2
519 #define CONFIG_GATEWAYIP 192.168.0.1
520 #define CONFIG_NETMASK 255.255.255.0
522 /* default location for tftp and bootm */
523 #define CONFIG_LOADADDR 1000000
525 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
527 #define CONFIG_BAUDRATE 115200
529 #define CONFIG_EXTRA_ENV_SETTINGS \
531 "consoledev=ttyS0\0" \
532 "ramdiskaddr=2000000\0" \
533 "ramdiskfile=uRamdisk\0" \
535 "dtbfile=sbc8641d.dtb\0" \
536 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
537 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
540 #define CONFIG_NFSBOOTCOMMAND \
541 "setenv bootargs root=/dev/nfs rw " \
542 "nfsroot=$serverip:$rootpath " \
543 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
544 "console=$consoledev,$baudrate $othbootargs;" \
545 "tftp $loadaddr $bootfile;" \
546 "tftp $dtbaddr $dtbfile;" \
547 "bootm $loadaddr - $dtbaddr"
549 #define CONFIG_RAMBOOTCOMMAND \
550 "setenv bootargs root=/dev/ram rw " \
551 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
552 "console=$consoledev,$baudrate $othbootargs;" \
553 "tftp $ramdiskaddr $ramdiskfile;" \
554 "tftp $loadaddr $bootfile;" \
555 "tftp $dtbaddr $dtbfile;" \
556 "bootm $loadaddr $ramdiskaddr $dtbaddr"
558 #define CONFIG_FLASHBOOTCOMMAND \
559 "setenv bootargs root=/dev/ram rw " \
560 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
561 "console=$consoledev,$baudrate $othbootargs;" \
562 "bootm ffd00000 ffb00000 ffa00000"
564 #define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND
566 #endif /* __CONFIG_H */