2 * Copyright 2007 Wind River Systems <www.windriver.com>
3 * Copyright 2007 Embedded Specialties, Inc.
4 * Joe Hamman <joe.hamman@embeddedspecialties.com>
6 * Copyright 2006 Freescale Semiconductor.
8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * SBC8641D board configuration file
32 * Make sure you change the MAC address and other network params first,
33 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
39 /* High Level Configuration Options */
40 #define CONFIG_MPC86xx 1 /* MPC86xx */
41 #define CONFIG_MPC8641 1 /* MPC8641 specific */
42 #define CONFIG_SBC8641D 1 /* SBC8641D board specific */
43 #define CONFIG_MP 1 /* support multiple processors */
44 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
46 #define CONFIG_SYS_TEXT_BASE 0xfff00000
49 #define CONFIG_SYS_DIAG_ADDR 0xff800000
52 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100
55 * virtual address to be used for temporary mappings. There
56 * should be 128k free at this VA.
58 #define CONFIG_SYS_SCRATCH_VA 0xe8000000
60 #define CONFIG_PCI 1 /* Enable PCIE */
61 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
62 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
63 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
64 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
66 #define CONFIG_TSEC_ENET /* tsec ethernet support */
67 #define CONFIG_ENV_OVERWRITE
69 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
70 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
72 #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/
73 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
74 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
75 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
76 #define CONFIG_NUM_DDR_CONTROLLERS 2
77 #define CACHE_LINE_INTERLEAVING 0x20000000
78 #define PAGE_INTERLEAVING 0x21000000
79 #define BANK_INTERLEAVING 0x22000000
80 #define SUPER_BANK_INTERLEAVING 0x23000000
83 #define CONFIG_ALTIVEC 1
86 * L2CR setup -- make sure this is right for your board!
90 #define L2_ENABLE (L2CR_L2E)
92 #ifndef CONFIG_SYS_CLK_FREQ
93 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
96 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
98 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
99 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
100 #define CONFIG_SYS_MEMTEST_END 0x00400000
103 * Base addresses -- Note these are effective addresses where the
104 * actual resources get mapped (not physical addresses)
106 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
107 #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
108 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
110 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
111 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
112 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
117 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
118 #define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */
119 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
120 #define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2
121 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
122 #define CONFIG_VERY_BIG_RAM
124 #define CONFIG_NUM_DDR_CONTROLLERS 2
125 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
126 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
128 #if defined(CONFIG_SPD_EEPROM)
130 * Determine DDR configuration from I2C interface.
132 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */
133 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */
134 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */
135 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */
139 * Manually set up DDR1 & DDR2 parameters
142 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
144 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
145 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
146 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000
147 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000
148 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
149 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
150 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
151 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
152 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
153 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
154 #define CONFIG_SYS_DDR_TIMING_1 0x38377322
155 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7
156 #define CONFIG_SYS_DDR_CFG_1A 0x43008008
157 #define CONFIG_SYS_DDR_CFG_2 0x24401000
158 #define CONFIG_SYS_DDR_MODE_1 0x23c00542
159 #define CONFIG_SYS_DDR_MODE_2 0x00000000
160 #define CONFIG_SYS_DDR_MODE_CTL 0x00000000
161 #define CONFIG_SYS_DDR_INTERVAL 0x05080100
162 #define CONFIG_SYS_DDR_DATA_INIT 0x00000000
163 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
164 #define CONFIG_SYS_DDR_CFG_1B 0xC3008008
166 #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F
167 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
168 #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000
169 #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000
170 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102
171 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000
172 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
173 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
174 #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000
175 #define CONFIG_SYS_DDR2_TIMING_0 0x00220802
176 #define CONFIG_SYS_DDR2_TIMING_1 0x38377322
177 #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7
178 #define CONFIG_SYS_DDR2_CFG_1A 0x43008008
179 #define CONFIG_SYS_DDR2_CFG_2 0x24401000
180 #define CONFIG_SYS_DDR2_MODE_1 0x23c00542
181 #define CONFIG_SYS_DDR2_MODE_2 0x00000000
182 #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000
183 #define CONFIG_SYS_DDR2_INTERVAL 0x05080100
184 #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000
185 #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000
186 #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008
191 /* #define CONFIG_ID_EEPROM 1
192 #define ID_EEPROM_ADDR 0x57 */
195 * The SBC8641D contains 16MB flash space at ff000000.
197 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
200 #define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */
201 #define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */
204 #define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */
205 #define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */
207 /* EPLD - User switches, board id, LEDs */
208 #define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */
209 #define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */
211 /* Local bus SDRAM 128MB */
212 #define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */
213 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */
214 #define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */
215 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */
217 /* Disk on Chip (DOC) 128MB */
218 #define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */
219 #define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */
222 #define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */
223 #define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
225 /* Control logic & misc peripherals */
226 #define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */
227 #define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
229 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
230 #define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */
232 #undef CONFIG_SYS_FLASH_CHECKSUM
233 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
234 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
235 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
236 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
238 #define CONFIG_FLASH_CFI_DRIVER
239 #define CONFIG_SYS_FLASH_CFI
240 #define CONFIG_SYS_WRITE_SWAPPED_DATA
241 #define CONFIG_SYS_FLASH_EMPTY_INFO
242 #define CONFIG_SYS_FLASH_PROTECTION
244 #undef CONFIG_CLOCKS_IN_MHZ
246 #define CONFIG_SYS_INIT_RAM_LOCK 1
247 #ifndef CONFIG_SYS_INIT_RAM_LOCK
248 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
250 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
252 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
254 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
255 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
257 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
258 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
261 #define CONFIG_CONS_INDEX 1
262 #define CONFIG_SYS_NS16550
263 #define CONFIG_SYS_NS16550_SERIAL
264 #define CONFIG_SYS_NS16550_REG_SIZE 1
265 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
267 #define CONFIG_SYS_BAUDRATE_TABLE \
268 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
270 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
271 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
273 /* Use the HUSH parser */
274 #define CONFIG_SYS_HUSH_PARSER
275 #ifdef CONFIG_SYS_HUSH_PARSER
276 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
280 * Pass open firmware flat tree to kernel
282 #define CONFIG_OF_LIBFDT 1
283 #define CONFIG_OF_BOARD_SETUP 1
284 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
289 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
290 #define CONFIG_HARD_I2C /* I2C with hardware support*/
291 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
292 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
293 #define CONFIG_SYS_I2C_SLAVE 0x7F
294 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
295 #define CONFIG_SYS_I2C_OFFSET 0x3100
300 #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */
301 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
302 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
306 * Addresses are mapped 1-1.
308 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
309 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
310 #define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS
311 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
312 #define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000
313 #define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS
314 #define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS
315 #define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */
317 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
318 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
319 #define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS
320 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
321 #define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000
322 #define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS
323 #define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS
324 #define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */
326 #if defined(CONFIG_PCI)
328 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
330 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
332 #define CONFIG_NET_MULTI
333 #define CONFIG_PCI_PNP /* do pci plug-and-play */
335 #undef CONFIG_EEPRO100
338 #if !defined(CONFIG_PCI_PNP)
339 #define PCI_ENET0_IOADDR 0xe0000000
340 #define PCI_ENET0_MEMADDR 0xe0000000
341 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
344 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
346 #define CONFIG_DOS_PARTITION
347 #undef CONFIG_SCSI_AHCI
349 #ifdef CONFIG_SCSI_AHCI
350 #define CONFIG_SATA_ULI5288
351 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
352 #define CONFIG_SYS_SCSI_MAX_LUN 1
353 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
354 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
357 #endif /* CONFIG_PCI */
359 #if defined(CONFIG_TSEC_ENET)
361 #ifndef CONFIG_NET_MULTI
362 #define CONFIG_NET_MULTI 1
365 /* #define CONFIG_MII 1 */ /* MII PHY management */
367 #define CONFIG_TSEC1 1
368 #define CONFIG_TSEC1_NAME "eTSEC1"
369 #define CONFIG_TSEC2 1
370 #define CONFIG_TSEC2_NAME "eTSEC2"
371 #define CONFIG_TSEC3 1
372 #define CONFIG_TSEC3_NAME "eTSEC3"
373 #define CONFIG_TSEC4 1
374 #define CONFIG_TSEC4_NAME "eTSEC4"
376 #define TSEC1_PHY_ADDR 0x1F
377 #define TSEC2_PHY_ADDR 0x00
378 #define TSEC3_PHY_ADDR 0x01
379 #define TSEC4_PHY_ADDR 0x02
380 #define TSEC1_PHYIDX 0
381 #define TSEC2_PHYIDX 0
382 #define TSEC3_PHYIDX 0
383 #define TSEC4_PHYIDX 0
384 #define TSEC1_FLAGS TSEC_GIGABIT
385 #define TSEC2_FLAGS TSEC_GIGABIT
386 #define TSEC3_FLAGS TSEC_GIGABIT
387 #define TSEC4_FLAGS TSEC_GIGABIT
389 #define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */
391 #define CONFIG_ETHPRIME "eTSEC1"
393 #endif /* CONFIG_TSEC_ENET */
396 * BAT0 2G Cacheable, non-guarded
399 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
400 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
401 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
402 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
405 * BAT1 1G Cache-inhibited, guarded
406 * 0x8000_0000 512M PCI-Express 1 Memory
407 * 0xa000_0000 512M PCI-Express 2 Memory
408 * Changed it for operating from 0xd0000000
410 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
411 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
412 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
413 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
414 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
417 * BAT2 512M Cache-inhibited, guarded
418 * 0xc000_0000 512M RapidIO Memory
420 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW \
421 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
422 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
423 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
424 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
427 * BAT3 4M Cache-inhibited, guarded
428 * 0xf800_0000 4M CCSR
430 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
431 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
432 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
433 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
434 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
436 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
437 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
438 | BATL_PP_RW | BATL_CACHEINHIBIT \
439 | BATL_GUARDEDSTORAGE)
440 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
441 | BATU_BL_1M | BATU_VS | BATU_VP)
442 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
443 | BATL_PP_RW | BATL_CACHEINHIBIT)
444 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
448 * BAT4 32M Cache-inhibited, guarded
449 * 0xe200_0000 16M PCI-Express 1 I/O
450 * 0xe300_0000 16M PCI-Express 2 I/0
451 * Note that this is at 0xe0000000
453 #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \
454 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
455 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
456 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
457 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
460 * BAT5 128K Cacheable, non-guarded
461 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
463 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
464 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
465 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
466 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
469 * BAT6 32M Cache-inhibited, guarded
470 * 0xfe00_0000 32M FLASH
472 #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
473 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
474 #define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
475 #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
476 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
478 /* Map the last 1M of flash where we're running from reset */
479 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
480 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
481 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
482 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
484 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
486 #define CONFIG_SYS_DBAT7L 0x00000000
487 #define CONFIG_SYS_DBAT7U 0x00000000
488 #define CONFIG_SYS_IBAT7L 0x00000000
489 #define CONFIG_SYS_IBAT7U 0x00000000
494 #define CONFIG_ENV_IS_IN_FLASH 1
495 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
496 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
497 #define CONFIG_ENV_SIZE 0x2000
499 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
500 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
502 #include <config_cmd_default.h>
503 #define CONFIG_CMD_PING
504 #define CONFIG_CMD_I2C
505 #define CONFIG_CMD_REGINFO
507 #if defined(CONFIG_PCI)
508 #define CONFIG_CMD_PCI
511 #undef CONFIG_WATCHDOG /* watchdog disabled */
514 * Miscellaneous configurable options
516 #define CONFIG_SYS_LONGHELP /* undef to save memory */
517 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
518 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
520 #if defined(CONFIG_CMD_KGDB)
521 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
523 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
526 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
527 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
528 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
529 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
532 * For booting Linux, the board info and command line data
533 * have to be in the first 8 MB of memory, since this is
534 * the maximum mapped by the Linux kernel during initialization.
536 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
538 /* Cache Configuration */
539 #define CONFIG_SYS_DCACHE_SIZE 32768
540 #define CONFIG_SYS_CACHELINE_SIZE 32
541 #if defined(CONFIG_CMD_KGDB)
542 #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
545 #if defined(CONFIG_CMD_KGDB)
546 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
547 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
551 * Environment Configuration
554 /* The mac addresses for all ethernet interface */
555 #if defined(CONFIG_TSEC_ENET)
556 #define CONFIG_ETHADDR 02:E0:0C:00:00:01
557 #define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD
558 #define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD
559 #define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD
562 #define CONFIG_HAS_ETH0 1
563 #define CONFIG_HAS_ETH1 1
564 #define CONFIG_HAS_ETH2 1
565 #define CONFIG_HAS_ETH3 1
567 #define CONFIG_IPADDR 192.168.0.50
569 #define CONFIG_HOSTNAME sbc8641d
570 #define CONFIG_ROOTPATH /opt/eldk/ppc_74xx
571 #define CONFIG_BOOTFILE uImage
573 #define CONFIG_SERVERIP 192.168.0.2
574 #define CONFIG_GATEWAYIP 192.168.0.1
575 #define CONFIG_NETMASK 255.255.255.0
577 /* default location for tftp and bootm */
578 #define CONFIG_LOADADDR 1000000
580 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
581 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
583 #define CONFIG_BAUDRATE 115200
585 #define CONFIG_EXTRA_ENV_SETTINGS \
587 "consoledev=ttyS0\0" \
588 "ramdiskaddr=2000000\0" \
589 "ramdiskfile=uRamdisk\0" \
591 "dtbfile=sbc8641d.dtb\0" \
592 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
593 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
596 #define CONFIG_NFSBOOTCOMMAND \
597 "setenv bootargs root=/dev/nfs rw " \
598 "nfsroot=$serverip:$rootpath " \
599 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
600 "console=$consoledev,$baudrate $othbootargs;" \
601 "tftp $loadaddr $bootfile;" \
602 "tftp $dtbaddr $dtbfile;" \
603 "bootm $loadaddr - $dtbaddr"
605 #define CONFIG_RAMBOOTCOMMAND \
606 "setenv bootargs root=/dev/ram rw " \
607 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
608 "console=$consoledev,$baudrate $othbootargs;" \
609 "tftp $ramdiskaddr $ramdiskfile;" \
610 "tftp $loadaddr $bootfile;" \
611 "tftp $dtbaddr $dtbfile;" \
612 "bootm $loadaddr $ramdiskaddr $dtbaddr"
614 #define CONFIG_FLASHBOOTCOMMAND \
615 "setenv bootargs root=/dev/ram rw " \
616 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
617 "console=$consoledev,$baudrate $othbootargs;" \
618 "bootm ffd00000 ffb00000 ffa00000"
620 #define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND
622 #endif /* __CONFIG_H */