2 * (C) Copyright 2002,2003 Motorola,Inc.
3 * Xianghua Xiao <X.Xiao@motorola.com>
5 * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
6 * Added support for Wind River SBC8560 board
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * sbc8560 board configuration file.
35 * Top level Makefile configuration choices
42 * High Level Configuration Options
44 #define CONFIG_BOOKE 1 /* BOOKE */
45 #define CONFIG_E500 1 /* BOOKE e500 family */
46 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
47 #define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
49 #define CONFIG_SYS_TEXT_BASE 0xfffc0000
52 #define CONFIG_CPM2 1 /* has CPM2 */
53 #define CONFIG_SBC8560 1 /* configuration for SBC8560 board */
54 #define CONFIG_MPC8560 1
56 /* XXX flagging this as something I might want to delete */
57 #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
59 #define CONFIG_TSEC_ENET /* tsec ethernet support */
60 #undef CONFIG_PCI /* pci ethernet support */
61 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
63 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
65 #define CONFIG_ENV_OVERWRITE
67 /* Using Localbus SDRAM to emulate flash before we can program the flash,
68 * normally you need a flash-boot image(u-boot.bin), if so undef this.
70 #undef CONFIG_RAM_AS_FLASH
72 #if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */
73 #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */
75 #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */
78 /* below can be toggled for performance analysis. otherwise use default */
79 #define CONFIG_L2_CACHE /* toggle L2 cache */
80 #undef CONFIG_BTB /* toggle branch predition */
82 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
83 #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
85 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
86 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
87 #define CONFIG_SYS_MEMTEST_END 0x00400000
89 #if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
90 defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
91 defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
92 #error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
96 * Base addresses -- Note these are effective addresses where the
97 * actual resources get mapped (not physical addresses)
99 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
102 #define CONFIG_SYS_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
104 #define CONFIG_SYS_CCSRBAR 0xff700000 /* default CCSRBAR */
106 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
107 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
109 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
112 #define CONFIG_FSL_DDR1
113 #undef CONFIG_FSL_DDR_INTERACTIVE
114 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
115 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
116 #undef CONFIG_DDR_SPD
118 #if defined(CONFIG_MPC85xx_REV1)
119 #define CONFIG_DDR_DLL /* possible DLL fix needed */
122 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
123 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
124 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
126 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
127 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
128 #define CONFIG_VERY_BIG_RAM
130 #define CONFIG_NUM_DDR_CONTROLLERS 1
131 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
132 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
134 /* I2C addresses of SPD EEPROMs */
135 #define SPD_EEPROM_ADDRESS 0x55 /* CTLR 0 DIMM 0 */
137 #undef CONFIG_CLOCKS_IN_MHZ
139 #if defined(CONFIG_RAM_AS_FLASH)
140 #define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
141 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
142 #define CONFIG_SYS_BR0_PRELIM 0xf8000801 /* port size 8bit */
143 #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */
144 #else /* Boot from real Flash */
145 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
146 #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
147 #define CONFIG_SYS_BR0_PRELIM 0xff800801 /* port size 8bit */
148 #define CONFIG_SYS_OR0_PRELIM 0xff800ff7 /* 8MB Flash */
150 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
152 /* local bus definitions */
153 #define CONFIG_SYS_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */
154 #define CONFIG_SYS_OR1_PRELIM 0xfc000ff7
156 #define CONFIG_SYS_BR2_PRELIM 0x00000000 /* CS2 not used */
157 #define CONFIG_SYS_OR2_PRELIM 0x00000000
159 #define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
160 #define CONFIG_SYS_OR3_PRELIM 0xfc000cc1
162 #if defined(CONFIG_RAM_AS_FLASH)
163 #define CONFIG_SYS_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */
165 #define CONFIG_SYS_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */
167 #define CONFIG_SYS_OR4_PRELIM 0xfc000cc1
169 #define CONFIG_SYS_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */
171 #define CONFIG_SYS_OR5_PRELIM 0xff000ff7
173 #define CONFIG_SYS_OR5_PRELIM 0xff0000f0
176 #define CONFIG_SYS_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */
177 #define CONFIG_SYS_OR6_PRELIM 0xfc000ff7
178 #define CONFIG_SYS_LBC_LCRR 0x00030002 /* local bus freq */
179 #define CONFIG_SYS_LBC_LBCR 0x00000000
180 #define CONFIG_SYS_LBC_LSRT 0x20000000
181 #define CONFIG_SYS_LBC_MRTPR 0x20000000
182 #define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
183 #define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
184 #define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
185 #define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
186 #define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
188 /* just hijack the MOT BCSR def for SBC8560 misc devices */
189 #define CONFIG_SYS_BCSR ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000)
190 /* the size of CS5 needs to be >= 16M for TLB and LAW setups */
192 #define CONFIG_SYS_INIT_RAM_LOCK 1
193 #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
194 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
196 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
197 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
198 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
200 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
201 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
204 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
205 #undef CONFIG_CONS_NONE /* define if console on something else */
207 #define CONFIG_CONS_INDEX 1
208 #define CONFIG_SYS_NS16550
209 #define CONFIG_SYS_NS16550_SERIAL
210 #define CONFIG_SYS_NS16550_REG_SIZE 1
211 #define CONFIG_SYS_NS16550_CLK 1843200 /* get_bus_freq(0) */
212 #define CONFIG_BAUDRATE 9600
214 #define CONFIG_SYS_BAUDRATE_TABLE \
215 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
217 #define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000)
218 #define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000)
220 /* Use the HUSH parser */
221 #define CONFIG_SYS_HUSH_PARSER
222 #ifdef CONFIG_SYS_HUSH_PARSER
223 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
226 /* pass open firmware flat tree */
227 #define CONFIG_OF_LIBFDT 1
228 #define CONFIG_OF_BOARD_SETUP 1
229 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
234 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
235 #define CONFIG_HARD_I2C /* I2C with hardware support*/
236 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
237 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
238 #define CONFIG_SYS_I2C_SLAVE 0x7F
239 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
240 #define CONFIG_SYS_I2C_OFFSET 0x3000
242 #define CONFIG_SYS_PCI_MEM_BASE 0xC0000000
243 #define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000
244 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
246 #ifdef CONFIG_TSEC_ENET
248 #ifndef CONFIG_NET_MULTI
249 #define CONFIG_NET_MULTI 1
253 #define CONFIG_MII 1 /* MII PHY management */
255 #define CONFIG_TSEC1 1
256 #define CONFIG_TSEC1_NAME "TSEC0"
257 #define CONFIG_TSEC2 1
258 #define CONFIG_TSEC2_NAME "TSEC1"
259 #define TSEC1_PHY_ADDR 0x19
260 #define TSEC2_PHY_ADDR 0x1a
261 #define TSEC1_PHYIDX 0
262 #define TSEC2_PHYIDX 0
263 #define TSEC1_FLAGS TSEC_GIGABIT
264 #define TSEC2_FLAGS TSEC_GIGABIT
266 /* Options are: TSEC[0-1] */
267 #define CONFIG_ETHPRIME "TSEC0"
269 #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
271 #undef CONFIG_ETHER_NONE /* define if ether on something else */
272 #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */
273 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
275 #if (CONFIG_ETHER_INDEX == 2)
279 * - Select bus for bd/buffers
282 #define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
283 #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
284 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
285 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
287 #elif (CONFIG_ETHER_INDEX == 3)
288 /* need more definitions here for FE3 */
289 #endif /* CONFIG_ETHER_INDEX */
291 #define CONFIG_MII /* MII PHY management */
292 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
294 * GPIO pins used for bit-banged MII communications
296 #define MDIO_PORT 2 /* Port C */
297 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
298 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
299 #define MDC_DECLARE MDIO_DECLARE
301 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
302 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
303 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
305 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
306 else iop->pdat &= ~0x00400000
308 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
309 else iop->pdat &= ~0x00200000
311 #define MIIDELAY udelay(1)
315 /*-----------------------------------------------------------------------
316 * FLASH and environment organization
319 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
320 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
322 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
323 #define CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */
325 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
326 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
328 #undef CONFIG_SYS_FLASH_CHECKSUM
329 #define CONFIG_SYS_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
330 #define CONFIG_SYS_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
332 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
335 /* XXX This doesn't work and I don't want to fix it */
336 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
337 #define CONFIG_SYS_RAMBOOT
339 #undef CONFIG_SYS_RAMBOOT
344 #if !defined(CONFIG_SYS_RAMBOOT)
345 #if defined(CONFIG_RAM_AS_FLASH)
346 #define CONFIG_ENV_IS_NOWHERE
347 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000)
348 #define CONFIG_ENV_SIZE 0x2000
350 #define CONFIG_ENV_IS_IN_FLASH 1
351 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
352 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
353 #define CONFIG_ENV_SIZE 0x2000 /* CONFIG_ENV_SECT_SIZE */
356 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
357 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
358 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
359 #define CONFIG_ENV_SIZE 0x2000
362 #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=dhcp console=ttyS0,9600"
363 /*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
364 #define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
366 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
367 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
373 #define CONFIG_BOOTP_BOOTFILESIZE
374 #define CONFIG_BOOTP_BOOTPATH
375 #define CONFIG_BOOTP_GATEWAY
376 #define CONFIG_BOOTP_HOSTNAME
380 * Command line configuration.
382 #include <config_cmd_default.h>
384 #define CONFIG_CMD_PING
385 #define CONFIG_CMD_I2C
386 #define CONFIG_CMD_REGINFO
388 #if defined(CONFIG_PCI)
389 #define CONFIG_CMD_PCI
392 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
393 #define CONFIG_CMD_MII
396 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
397 #undef CONFIG_CMD_SAVEENV
398 #undef CONFIG_CMD_LOADS
402 #undef CONFIG_WATCHDOG /* watchdog disabled */
405 * Miscellaneous configurable options
407 #define CONFIG_SYS_LONGHELP /* undef to save memory */
408 #define CONFIG_SYS_PROMPT "SBC8560=> " /* Monitor Command Prompt */
409 #if defined(CONFIG_CMD_KGDB)
410 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
412 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
414 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
415 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
416 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
417 #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
418 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
421 * For booting Linux, the board info and command line data
422 * have to be in the first 8 MB of memory, since this is
423 * the maximum mapped by the Linux kernel during initialization.
425 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
427 #if defined(CONFIG_CMD_KGDB)
428 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
429 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
432 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
433 #define CONFIG_HAS_ETH0
434 #define CONFIG_HAS_ETH1
437 /* You can compile in a MAC address and your custom net settings by using
438 * the following syntax. Your board should be marked with the assigned
439 * MAC addresses directly on it.
441 * #define CONFIG_ETHADDR de:ad:be:ef:00:00
442 * #define CONFIG_ETH1ADDR fa:ke:ad:dr:es:s!
443 * #define CONFIG_SERVERIP <server ip>
444 * #define CONFIG_IPADDR <board ip>
445 * #define CONFIG_GATEWAYIP <gateway ip>
446 * #define CONFIG_NETMASK <your netmask>
449 #define CONFIG_HOSTNAME SBC8560
450 #define CONFIG_ROOTPATH /home/ppc
451 #define CONFIG_BOOTFILE uImage
453 #define CONFIG_EXTRA_ENV_SETTINGS \
455 "consoledev=ttyS0\0" \
456 "ramdiskaddr=2000000\0" \
457 "ramdiskfile=ramdisk.uboot\0" \
459 "fdtfile=sbc8560.dtb\0"
461 #define CONFIG_NFSBOOTCOMMAND \
462 "setenv bootargs root=/dev/nfs rw " \
463 "nfsroot=$serverip:$rootpath " \
464 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
465 "console=$consoledev,$baudrate $othbootargs;" \
466 "tftp $loadaddr $bootfile;" \
467 "tftp $fdtaddr $fdtfile;" \
468 "bootm $loadaddr - $fdtaddr"
471 #define CONFIG_RAMBOOTCOMMAND \
472 "setenv bootargs root=/dev/ram rw " \
473 "console=$consoledev,$baudrate $othbootargs;" \
474 "tftp $ramdiskaddr $ramdiskfile;" \
475 "tftp $loadaddr $bootfile;" \
476 "tftp $fdtaddr $fdtfile;" \
477 "bootm $loadaddr $ramdiskaddr $fdtaddr"
479 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
481 #endif /* __CONFIG_H */