include/configs/sbc8349.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * WindRiver SBC8349 U-Boot configuration file.
   4  * Copyright (c) 2006, 2007 Wind River Systems, Inc.
   5  *
   6  * Paul Gortmaker <paul.gortmaker@windriver.com>
   7  * Based on the MPC8349EMDS config.
   8  */
   9
  10 /*
  11  * sbc8349 board configuration file.
  12  */
  13
  14 #ifndef __CONFIG_H
  15 #define __CONFIG_H
  16
  17 /*
  18  * High Level Configuration Options
  19  */
  20 #define CONFIG_E300             1       /* E300 Family */
  21
  22 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
  23 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
  24
  25 #define CONFIG_SYS_IMMR         0xE0000000
  26
  27 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  28 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  29 #define CONFIG_SYS_MEMTEST_END          0x00100000
  30
  31 /*
  32  * DDR Setup
  33  */
  34 #undef CONFIG_DDR_ECC                   /* only for ECC DDR module */
  35 #undef CONFIG_DDR_ECC_CMD               /* use DDR ECC user commands */
  36 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  37 #define CONFIG_SYS_83XX_DDR_USES_CS0    /* WRS; Fsl board uses CS2/CS3 */
  38
  39 /*
  40  * 32-bit data path mode.
  41  *
  42  * Please note that using this mode for devices with the real density of 64-bit
  43  * effectively reduces the amount of available memory due to the effect of
  44  * wrapping around while translating address to row/columns, for example in the
  45  * 256MB module the upper 128MB get aliased with contents of the lower
  46  * 128MB); normally this define should be used for devices with real 32-bit
  47  * data path.
  48  */
  49 #undef CONFIG_DDR_32BIT
  50
  51 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
  52 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  53 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  54 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  55                                 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  56 #define CONFIG_DDR_2T_TIMING
  57
  58 #if defined(CONFIG_SPD_EEPROM)
  59 /*
  60  * Determine DDR configuration from I2C interface.
  61  */
  62 #define SPD_EEPROM_ADDRESS      0x52            /* DDR DIMM */
  63
  64 #else
  65 /*
  66  * Manually set up DDR parameters
  67  * NB: manual DDR setup untested on sbc834x
  68  */
  69 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
  70 #define CONFIG_SYS_DDR_CS2_CONFIG       (CSCONFIG_EN \
  71                                         | CSCONFIG_ROW_BIT_13 \
  72                                         | CSCONFIG_COL_BIT_10)
  73 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
  74 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
  75 #define CONFIG_SYS_DDR_CONTROL  0xc2000000      /* unbuffered,no DYN_PWR */
  76 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
  77
  78 #if defined(CONFIG_DDR_32BIT)
  79 /* set burst length to 8 for 32-bit data path */
  80                                 /* DLL,normal,seq,4/2.5, 8 burst len */
  81 #define CONFIG_SYS_DDR_MODE     0x00000023
  82 #else
  83 /* the default burst length is 4 - for 64-bit data path */
  84                                 /* DLL,normal,seq,4/2.5, 4 burst len */
  85 #define CONFIG_SYS_DDR_MODE     0x00000022
  86 #endif
  87 #endif
  88
  89 /*
  90  * SDRAM on the Local Bus
  91  */
  92 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* Localbus SDRAM */
  93 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
  94
  95 /*
  96  * FLASH on the Local Bus
  97  */
  98 #define CONFIG_SYS_FLASH_BASE           0xFF800000      /* start of FLASH   */
  99 #define CONFIG_SYS_FLASH_SIZE           8               /* flash size in MB */
 100
 101 /* FLASH */
 102 #define CONFIG_SYS_BR0_PRELIM           (0xFF800000 | BR_PS_16 | BR_MS_GPCM | BR_V)
 103 #define CONFIG_SYS_OR0_PRELIM           (OR_AM_8MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
 104
 105 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 106 #define CONFIG_SYS_MAX_FLASH_SECT       64      /* sectors per device */
 107
 108 #undef CONFIG_SYS_FLASH_CHECKSUM
 109 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 110 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 111
 112 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 113
 114 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 115 #define CONFIG_SYS_RAMBOOT
 116 #else
 117 #undef  CONFIG_SYS_RAMBOOT
 118 #endif
 119
 120 #define CONFIG_SYS_INIT_RAM_LOCK        1
 121                                         /* Initial RAM address */
 122 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000
 123                                         /* Size of used area in RAM*/
 124 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000
 125
 126 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 127                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 128 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 129
 130 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024)    /* Reserve 256 kB for Mon */
 131 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 132
 133 /*
 134  * Local Bus LCRR and LBCR regs
 135  *    LCRR:  DLL bypass, Clock divider is 4
 136  * External Local Bus rate is
 137  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 138  */
 139 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 140 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 141 #define CONFIG_SYS_LBC_LBCR     0x00000000
 142
 143 #undef CONFIG_SYS_LB_SDRAM      /* if board has SDRAM on local bus */
 144
 145 #ifdef CONFIG_SYS_LB_SDRAM
 146 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
 147 /*
 148  * Base Register 2 and Option Register 2 configure SDRAM.
 149  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 150  *
 151  * For BR2, need:
 152  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 153  *    port-size = 32-bits = BR2[19:20] = 11
 154  *    no parity checking = BR2[21:22] = 00
 155  *    SDRAM for MSEL = BR2[24:26] = 011
 156  *    Valid = BR[31] = 1
 157  *
 158  * 0    4    8    12   16   20   24   28
 159  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
 160  */
 161
 162 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_LBC_SDRAM_BASE \
 163                                         | BR_PS_32 \
 164                                         | BR_MS_SDRAM \
 165                                         | BR_V)
 166                                         /* 0xF0001861 */
 167 /*
 168  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 169  *
 170  * For OR2, need:
 171  *    64MB mask for AM, OR2[0:7] = 1111 1100
 172  *                 XAM, OR2[17:18] = 11
 173  *    9 columns OR2[19-21] = 010
 174  *    13 rows   OR2[23-25] = 100
 175  *    EAD set for extra time OR[31] = 1
 176  *
 177  * 0    4    8    12   16   20   24   28
 178  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
 179  */
 180
 181 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_64MB \
 182                         | OR_SDRAM_XAM \
 183                         | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
 184                         | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
 185                         | OR_SDRAM_EAD)
 186                         /* 0xFC006901 */
 187
 188                                 /* LB sdram refresh timer, about 6us */
 189 #define CONFIG_SYS_LBC_LSRT     0x32000000
 190                                 /* LB refresh timer prescal, 266MHz/32 */
 191 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 192
 193 #define CONFIG_SYS_LBC_LSDMR_COMMON     (LSDMR_RFEN \
 194                                         | LSDMR_BSMA1516 \
 195                                         | LSDMR_RFCR8 \
 196                                         | LSDMR_PRETOACT6 \
 197                                         | LSDMR_ACTTORW3 \
 198                                         | LSDMR_BL8 \
 199                                         | LSDMR_WRC3 \
 200                                         | LSDMR_CL3)
 201
 202 /*
 203  * SDRAM Controller configuration sequence.
 204  */
 205 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 206 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 207 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 208 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 209 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 210 #endif
 211
 212 /*
 213  * Serial Port
 214  */
 215 #define CONFIG_SYS_NS16550_SERIAL
 216 #define CONFIG_SYS_NS16550_REG_SIZE    1
 217 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 218
 219 #define CONFIG_SYS_BAUDRATE_TABLE  \
 220                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 221
 222 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 223 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 224
 225 /* I2C */
 226 #define CONFIG_SYS_I2C
 227 #define CONFIG_SYS_I2C_FSL
 228 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 229 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 230 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 231 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 232 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 233 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 234 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69}, {1, 0x69} }
 235 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
 236
 237 /* TSEC */
 238 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 239 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 240 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 241 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 242
 243 /*
 244  * General PCI
 245  * Addresses are mapped 1-1.
 246  */
 247 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 248 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 249 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 250 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 251 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 252 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 253 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 254 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 255 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 256
 257 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 258 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 259 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 260 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 261 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 262 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 263 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 264 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 265 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 266
 267 #if defined(CONFIG_PCI)
 268
 269 #undef CONFIG_EEPRO100
 270 #undef CONFIG_TULIP
 271
 272 #if !defined(CONFIG_PCI_PNP)
 273         #define PCI_ENET0_IOADDR        0xFIXME
 274         #define PCI_ENET0_MEMADDR       0xFIXME
 275         #define PCI_IDSEL_NUMBER        0xFIXME
 276 #endif
 277
 278 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 279 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 280
 281 #endif  /* CONFIG_PCI */
 282
 283 /*
 284  * TSEC configuration
 285  */
 286
 287 #if defined(CONFIG_TSEC_ENET)
 288
 289 #define CONFIG_TSEC1    1
 290 #define CONFIG_TSEC1_NAME       "TSEC0"
 291 #define CONFIG_TSEC2    1
 292 #define CONFIG_TSEC2_NAME       "TSEC1"
 293 #define CONFIG_PHY_BCM5421S     1
 294 #define TSEC1_PHY_ADDR          0x19
 295 #define TSEC2_PHY_ADDR          0x1a
 296 #define TSEC1_PHYIDX            0
 297 #define TSEC2_PHYIDX            0
 298 #define TSEC1_FLAGS             TSEC_GIGABIT
 299 #define TSEC2_FLAGS             TSEC_GIGABIT
 300
 301 /* Options are: TSEC[0-1] */
 302 #define CONFIG_ETHPRIME         "TSEC0"
 303
 304 #endif  /* CONFIG_TSEC_ENET */
 305
 306 /*
 307  * Environment
 308  */
 309 #ifndef CONFIG_SYS_RAMBOOT
 310         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 311         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 312         #define CONFIG_ENV_SIZE         0x2000
 313
 314 /* Address and size of Redundant Environment Sector     */
 315 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 316 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 317
 318 #else
 319         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 320         #define CONFIG_ENV_SIZE         0x2000
 321 #endif
 322
 323 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 324 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 325
 326 /*
 327  * BOOTP options
 328  */
 329 #define CONFIG_BOOTP_BOOTFILESIZE
 330
 331 /*
 332  * Command line configuration.
 333  */
 334
 335 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 336
 337 /*
 338  * Miscellaneous configurable options
 339  */
 340 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 341
 342 /*
 343  * For booting Linux, the board info and command line data
 344  * have to be in the first 256 MB of memory, since this is
 345  * the maximum mapped by the Linux kernel during initialization.
 346  */
 347                                 /* Initial Memory map for Linux*/
 348 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 349
 350 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 351
 352 /* System IO Config */
 353 #define CONFIG_SYS_SICRH 0
 354 #define CONFIG_SYS_SICRL SICRL_LDP_A
 355
 356 #define CONFIG_SYS_HID0_INIT    0x000000000
 357 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
 358                                 | HID0_ENABLE_INSTRUCTION_CACHE)
 359
 360 /* #define CONFIG_SYS_HID0_FINAL        (\
 361         HID0_ENABLE_INSTRUCTION_CACHE |\
 362         HID0_ENABLE_M_BIT |\
 363         HID0_ENABLE_ADDRESS_BROADCAST) */
 364
 365 #define CONFIG_SYS_HID2 HID2_HBE
 366
 367 #ifdef CONFIG_PCI
 368 #define CONFIG_PCI_INDIRECT_BRIDGE
 369 #endif
 370
 371 #if defined(CONFIG_CMD_KGDB)
 372 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 373 #endif
 374
 375 /*
 376  * Environment Configuration
 377  */
 378 #define CONFIG_ENV_OVERWRITE
 379
 380 #if defined(CONFIG_TSEC_ENET)
 381 #define CONFIG_HAS_ETH0
 382 #define CONFIG_HAS_ETH1
 383 #endif
 384
 385 #define CONFIG_HOSTNAME         "SBC8349"
 386 #define CONFIG_ROOTPATH         "/tftpboot/rootfs"
 387 #define CONFIG_BOOTFILE         "uImage"
 388
 389                                 /* default location for tftp and bootm */
 390 #define CONFIG_LOADADDR         800000
 391
 392 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 393         "netdev=eth0\0"                                                 \
 394         "hostname=sbc8349\0"                                            \
 395         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 396                 "nfsroot=${serverip}:${rootpath}\0"                     \
 397         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 398         "addip=setenv bootargs ${bootargs} "                            \
 399                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 400                 ":${hostname}:${netdev}:off panic=1\0"                  \
 401         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 402         "flash_nfs=run nfsargs addip addtty;"                           \
 403                 "bootm ${kernel_addr}\0"                                \
 404         "flash_self=run ramargs addip addtty;"                          \
 405                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 406         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 407                 "bootm\0"                                               \
 408         "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0"               \
 409         "update=protect off ff800000 ff83ffff; "                        \
 410                 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
 411         "upd=run load update\0"                                         \
 412         "fdtaddr=780000\0"                                              \
 413         "fdtfile=sbc8349.dtb\0"                                         \
 414         ""
 415
 416 #define CONFIG_NFSBOOTCOMMAND                                           \
 417         "setenv bootargs root=/dev/nfs rw "                             \
 418                 "nfsroot=$serverip:$rootpath "                          \
 419                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 420                                                         "$netdev:off "  \
 421                 "console=$consoledev,$baudrate $othbootargs;"           \
 422         "tftp $loadaddr $bootfile;"                                     \
 423         "tftp $fdtaddr $fdtfile;"                                       \
 424         "bootm $loadaddr - $fdtaddr"
 425
 426 #define CONFIG_RAMBOOTCOMMAND                                           \
 427         "setenv bootargs root=/dev/ram rw "                             \
 428                 "console=$consoledev,$baudrate $othbootargs;"           \
 429         "tftp $ramdiskaddr $ramdiskfile;"                               \
 430         "tftp $loadaddr $bootfile;"                                     \
 431         "tftp $fdtaddr $fdtfile;"                                       \
 432         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 433
 434 #define CONFIG_BOOTCOMMAND      "run flash_self"
 435
 436 #endif  /* __CONFIG_H */