Merge branch '2019-05-24-master-imports'
[platform/kernel/u-boot.git] / include / configs / sbc8349.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * WindRiver SBC8349 U-Boot configuration file.
4  * Copyright (c) 2006, 2007 Wind River Systems, Inc.
5  *
6  * Paul Gortmaker <paul.gortmaker@windriver.com>
7  * Based on the MPC8349EMDS config.
8  */
9
10 /*
11  * sbc8349 board configuration file.
12  */
13
14 #ifndef __CONFIG_H
15 #define __CONFIG_H
16
17 /*
18  * High Level Configuration Options
19  */
20 #define CONFIG_E300             1       /* E300 Family */
21
22 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
23 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
24
25 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
26 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
27 #define CONFIG_SYS_MEMTEST_END          0x00100000
28
29 /*
30  * DDR Setup
31  */
32 #undef CONFIG_DDR_ECC                   /* only for ECC DDR module */
33 #undef CONFIG_DDR_ECC_CMD               /* use DDR ECC user commands */
34 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
35 #define CONFIG_SYS_83XX_DDR_USES_CS0    /* WRS; Fsl board uses CS2/CS3 */
36
37 /*
38  * 32-bit data path mode.
39  *
40  * Please note that using this mode for devices with the real density of 64-bit
41  * effectively reduces the amount of available memory due to the effect of
42  * wrapping around while translating address to row/columns, for example in the
43  * 256MB module the upper 128MB get aliased with contents of the lower
44  * 128MB); normally this define should be used for devices with real 32-bit
45  * data path.
46  */
47 #undef CONFIG_DDR_32BIT
48
49 #define CONFIG_SYS_SDRAM_BASE           0x00000000 /* DDR is system memory*/
50 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
51                                 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
52 #define CONFIG_DDR_2T_TIMING
53
54 #if defined(CONFIG_SPD_EEPROM)
55 /*
56  * Determine DDR configuration from I2C interface.
57  */
58 #define SPD_EEPROM_ADDRESS      0x52            /* DDR DIMM */
59
60 #else
61 /*
62  * Manually set up DDR parameters
63  * NB: manual DDR setup untested on sbc834x
64  */
65 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
66 #define CONFIG_SYS_DDR_CS2_CONFIG       (CSCONFIG_EN \
67                                         | CSCONFIG_ROW_BIT_13 \
68                                         | CSCONFIG_COL_BIT_10)
69 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
70 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
71 #define CONFIG_SYS_DDR_CONTROL  0xc2000000      /* unbuffered,no DYN_PWR */
72 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
73
74 #if defined(CONFIG_DDR_32BIT)
75 /* set burst length to 8 for 32-bit data path */
76                                 /* DLL,normal,seq,4/2.5, 8 burst len */
77 #define CONFIG_SYS_DDR_MODE     0x00000023
78 #else
79 /* the default burst length is 4 - for 64-bit data path */
80                                 /* DLL,normal,seq,4/2.5, 4 burst len */
81 #define CONFIG_SYS_DDR_MODE     0x00000022
82 #endif
83 #endif
84
85 /*
86  * SDRAM on the Local Bus
87  */
88 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* Localbus SDRAM */
89 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
90
91 /*
92  * FLASH on the Local Bus
93  */
94 #define CONFIG_SYS_FLASH_BASE           0xFF800000      /* start of FLASH   */
95 #define CONFIG_SYS_FLASH_SIZE           8               /* flash size in MB */
96
97
98 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
99 #define CONFIG_SYS_MAX_FLASH_SECT       64      /* sectors per device */
100
101 #undef CONFIG_SYS_FLASH_CHECKSUM
102 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
103 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
104
105 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
106
107 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
108 #define CONFIG_SYS_RAMBOOT
109 #else
110 #undef  CONFIG_SYS_RAMBOOT
111 #endif
112
113 #define CONFIG_SYS_INIT_RAM_LOCK        1
114                                         /* Initial RAM address */
115 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000
116                                         /* Size of used area in RAM*/
117 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000
118
119 #define CONFIG_SYS_GBL_DATA_OFFSET      \
120                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
121 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
122
123 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024)    /* Reserve 256 kB for Mon */
124 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
125
126 #undef CONFIG_SYS_LB_SDRAM      /* if board has SDRAM on local bus */
127
128 /*
129  * Serial Port
130  */
131 #define CONFIG_SYS_NS16550_SERIAL
132 #define CONFIG_SYS_NS16550_REG_SIZE    1
133 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
134
135 #define CONFIG_SYS_BAUDRATE_TABLE  \
136                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
137
138 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
139 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
140
141 /* I2C */
142 #define CONFIG_SYS_I2C
143 #define CONFIG_SYS_I2C_FSL
144 #define CONFIG_SYS_FSL_I2C_SPEED        400000
145 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
146 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
147 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
148 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
149 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
150 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69}, {1, 0x69} }
151 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
152
153 /* TSEC */
154 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
155 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
156 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
157 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
158
159 /*
160  * General PCI
161  * Addresses are mapped 1-1.
162  */
163 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
164 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
165 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
166 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
167 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
168 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
169 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
170 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
171 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
172
173 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
174 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
175 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
176 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
177 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
178 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
179 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
180 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
181 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
182
183 #if defined(CONFIG_PCI)
184
185 #undef CONFIG_EEPRO100
186 #undef CONFIG_TULIP
187
188 #if !defined(CONFIG_PCI_PNP)
189         #define PCI_ENET0_IOADDR        0xFIXME
190         #define PCI_ENET0_MEMADDR       0xFIXME
191         #define PCI_IDSEL_NUMBER        0xFIXME
192 #endif
193
194 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
195 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
196
197 #endif  /* CONFIG_PCI */
198
199 /*
200  * TSEC configuration
201  */
202
203 #if defined(CONFIG_TSEC_ENET)
204
205 #define CONFIG_TSEC1    1
206 #define CONFIG_TSEC1_NAME       "TSEC0"
207 #define CONFIG_TSEC2    1
208 #define CONFIG_TSEC2_NAME       "TSEC1"
209 #define CONFIG_PHY_BCM5421S     1
210 #define TSEC1_PHY_ADDR          0x19
211 #define TSEC2_PHY_ADDR          0x1a
212 #define TSEC1_PHYIDX            0
213 #define TSEC2_PHYIDX            0
214 #define TSEC1_FLAGS             TSEC_GIGABIT
215 #define TSEC2_FLAGS             TSEC_GIGABIT
216
217 /* Options are: TSEC[0-1] */
218 #define CONFIG_ETHPRIME         "TSEC0"
219
220 #endif  /* CONFIG_TSEC_ENET */
221
222 /*
223  * Environment
224  */
225 #ifndef CONFIG_SYS_RAMBOOT
226         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
227         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
228         #define CONFIG_ENV_SIZE         0x2000
229
230 /* Address and size of Redundant Environment Sector     */
231 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
232 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
233
234 #else
235         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
236         #define CONFIG_ENV_SIZE         0x2000
237 #endif
238
239 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
240 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
241
242 /*
243  * BOOTP options
244  */
245 #define CONFIG_BOOTP_BOOTFILESIZE
246
247 /*
248  * Command line configuration.
249  */
250
251 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
252
253 /*
254  * Miscellaneous configurable options
255  */
256 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
257
258 /*
259  * For booting Linux, the board info and command line data
260  * have to be in the first 256 MB of memory, since this is
261  * the maximum mapped by the Linux kernel during initialization.
262  */
263                                 /* Initial Memory map for Linux*/
264 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
265
266 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
267
268 /* System IO Config */
269 #define CONFIG_SYS_SICRH 0
270 #define CONFIG_SYS_SICRL SICRL_LDP_A
271
272 #ifdef CONFIG_PCI
273 #define CONFIG_PCI_INDIRECT_BRIDGE
274 #endif
275
276 #if defined(CONFIG_CMD_KGDB)
277 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
278 #endif
279
280 /*
281  * Environment Configuration
282  */
283 #define CONFIG_ENV_OVERWRITE
284
285 #if defined(CONFIG_TSEC_ENET)
286 #define CONFIG_HAS_ETH0
287 #define CONFIG_HAS_ETH1
288 #endif
289
290 #define CONFIG_HOSTNAME         "SBC8349"
291 #define CONFIG_ROOTPATH         "/tftpboot/rootfs"
292 #define CONFIG_BOOTFILE         "uImage"
293
294                                 /* default location for tftp and bootm */
295 #define CONFIG_LOADADDR         800000
296
297 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
298         "netdev=eth0\0"                                                 \
299         "hostname=sbc8349\0"                                            \
300         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
301                 "nfsroot=${serverip}:${rootpath}\0"                     \
302         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
303         "addip=setenv bootargs ${bootargs} "                            \
304                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
305                 ":${hostname}:${netdev}:off panic=1\0"                  \
306         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
307         "flash_nfs=run nfsargs addip addtty;"                           \
308                 "bootm ${kernel_addr}\0"                                \
309         "flash_self=run ramargs addip addtty;"                          \
310                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
311         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
312                 "bootm\0"                                               \
313         "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0"               \
314         "update=protect off ff800000 ff83ffff; "                        \
315                 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
316         "upd=run load update\0"                                         \
317         "fdtaddr=780000\0"                                              \
318         "fdtfile=sbc8349.dtb\0"                                         \
319         ""
320
321 #define CONFIG_NFSBOOTCOMMAND                                           \
322         "setenv bootargs root=/dev/nfs rw "                             \
323                 "nfsroot=$serverip:$rootpath "                          \
324                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
325                                                         "$netdev:off "  \
326                 "console=$consoledev,$baudrate $othbootargs;"           \
327         "tftp $loadaddr $bootfile;"                                     \
328         "tftp $fdtaddr $fdtfile;"                                       \
329         "bootm $loadaddr - $fdtaddr"
330
331 #define CONFIG_RAMBOOTCOMMAND                                           \
332         "setenv bootargs root=/dev/ram rw "                             \
333                 "console=$consoledev,$baudrate $othbootargs;"           \
334         "tftp $ramdiskaddr $ramdiskfile;"                               \
335         "tftp $loadaddr $bootfile;"                                     \
336         "tftp $fdtaddr $fdtfile;"                                       \
337         "bootm $loadaddr $ramdiskaddr $fdtaddr"
338
339 #define CONFIG_BOOTCOMMAND      "run flash_self"
340
341 #endif  /* __CONFIG_H */