include/configs/sbc8349.h

   1 /*
   2  * WindRiver SBC8349 U-Boot configuration file.
   3  * Copyright (c) 2006, 2007 Wind River Systems, Inc.
   4  *
   5  * Paul Gortmaker <paul.gortmaker@windriver.com>
   6  * Based on the MPC8349EMDS config.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /*
  12  * sbc8349 board configuration file.
  13  */
  14
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 /*
  19  * High Level Configuration Options
  20  */
  21 #define CONFIG_E300             1       /* E300 Family */
  22 #define CONFIG_MPC834x          1       /* MPC834x family */
  23 #define CONFIG_MPC8349          1       /* MPC8349 specific */
  24 #define CONFIG_SBC8349          1       /* WRS SBC8349 board specific */
  25
  26 #define CONFIG_SYS_TEXT_BASE    0xFF800000
  27
  28 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
  29 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
  30
  31 /*
  32  * The default if PCI isn't enabled, or if no PCI clk setting is given
  33  * is 66MHz; this is what the board defaults to when the PCI slot is
  34  * physically empty.  The board will automatically (i.e w/o jumpers)
  35  * clock down to 33MHz if you insert a 33MHz PCI card.
  36  */
  37 #ifdef CONFIG_PCI_33M
  38 #define CONFIG_83XX_CLKIN       33000000        /* in Hz */
  39 #else   /* 66M */
  40 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  41 #endif
  42
  43 #ifndef CONFIG_SYS_CLK_FREQ
  44 #ifdef CONFIG_PCI_33M
  45 #define CONFIG_SYS_CLK_FREQ     33000000
  46 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_8X1
  47 #else   /* 66M */
  48 #define CONFIG_SYS_CLK_FREQ     66000000
  49 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_4X1
  50 #endif
  51 #endif
  52
  53 #undef CONFIG_BOARD_EARLY_INIT_F                /* call board_pre_init */
  54
  55 #define CONFIG_SYS_IMMR         0xE0000000
  56
  57 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  58 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  59 #define CONFIG_SYS_MEMTEST_END          0x00100000
  60
  61 /*
  62  * DDR Setup
  63  */
  64 #undef CONFIG_DDR_ECC                   /* only for ECC DDR module */
  65 #undef CONFIG_DDR_ECC_CMD               /* use DDR ECC user commands */
  66 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  67 #define CONFIG_SYS_83XX_DDR_USES_CS0    /* WRS; Fsl board uses CS2/CS3 */
  68
  69 /*
  70  * 32-bit data path mode.
  71  *
  72  * Please note that using this mode for devices with the real density of 64-bit
  73  * effectively reduces the amount of available memory due to the effect of
  74  * wrapping around while translating address to row/columns, for example in the
  75  * 256MB module the upper 128MB get aliased with contents of the lower
  76  * 128MB); normally this define should be used for devices with real 32-bit
  77  * data path.
  78  */
  79 #undef CONFIG_DDR_32BIT
  80
  81 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
  82 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  83 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  84 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  85                                 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  86 #define CONFIG_DDR_2T_TIMING
  87
  88 #if defined(CONFIG_SPD_EEPROM)
  89 /*
  90  * Determine DDR configuration from I2C interface.
  91  */
  92 #define SPD_EEPROM_ADDRESS      0x52            /* DDR DIMM */
  93
  94 #else
  95 /*
  96  * Manually set up DDR parameters
  97  * NB: manual DDR setup untested on sbc834x
  98  */
  99 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
 100 #define CONFIG_SYS_DDR_CS2_CONFIG       (CSCONFIG_EN \
 101                                         | CSCONFIG_ROW_BIT_13 \
 102                                         | CSCONFIG_COL_BIT_10)
 103 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
 104 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
 105 #define CONFIG_SYS_DDR_CONTROL  0xc2000000      /* unbuffered,no DYN_PWR */
 106 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
 107
 108 #if defined(CONFIG_DDR_32BIT)
 109 /* set burst length to 8 for 32-bit data path */
 110                                 /* DLL,normal,seq,4/2.5, 8 burst len */
 111 #define CONFIG_SYS_DDR_MODE     0x00000023
 112 #else
 113 /* the default burst length is 4 - for 64-bit data path */
 114                                 /* DLL,normal,seq,4/2.5, 4 burst len */
 115 #define CONFIG_SYS_DDR_MODE     0x00000022
 116 #endif
 117 #endif
 118
 119 /*
 120  * SDRAM on the Local Bus
 121  */
 122 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* Localbus SDRAM */
 123 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 124
 125 /*
 126  * FLASH on the Local Bus
 127  */
 128 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 129 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 130 #define CONFIG_SYS_FLASH_BASE           0xFF800000      /* start of FLASH   */
 131 #define CONFIG_SYS_FLASH_SIZE           8               /* flash size in MB */
 132 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 133
 134 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE \
 135                                         | BR_PS_16      /* 16 bit port */ \
 136                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 137                                         | BR_V)         /* valid */
 138
 139 #define CONFIG_SYS_OR0_PRELIM           (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 140                                         | OR_GPCM_XAM \
 141                                         | OR_GPCM_CSNT \
 142                                         | OR_GPCM_ACS_DIV2 \
 143                                         | OR_GPCM_XACS \
 144                                         | OR_GPCM_SCY_15 \
 145                                         | OR_GPCM_TRLX_SET \
 146                                         | OR_GPCM_EHTR_SET \
 147                                         | OR_GPCM_EAD)
 148                                         /* 0xFF806FF7 */
 149
 150                                         /* window base at flash base */
 151 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 152 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 153
 154 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 155 #define CONFIG_SYS_MAX_FLASH_SECT       64      /* sectors per device */
 156
 157 #undef CONFIG_SYS_FLASH_CHECKSUM
 158 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 159 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 160
 161 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 162
 163 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 164 #define CONFIG_SYS_RAMBOOT
 165 #else
 166 #undef  CONFIG_SYS_RAMBOOT
 167 #endif
 168
 169 #define CONFIG_SYS_INIT_RAM_LOCK        1
 170                                         /* Initial RAM address */
 171 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000
 172                                         /* Size of used area in RAM*/
 173 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000
 174
 175 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 176                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 177 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 178
 179 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024)    /* Reserve 256 kB for Mon */
 180 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 181
 182 /*
 183  * Local Bus LCRR and LBCR regs
 184  *    LCRR:  DLL bypass, Clock divider is 4
 185  * External Local Bus rate is
 186  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 187  */
 188 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 189 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 190 #define CONFIG_SYS_LBC_LBCR     0x00000000
 191
 192 #undef CONFIG_SYS_LB_SDRAM      /* if board has SDRAM on local bus */
 193
 194 #ifdef CONFIG_SYS_LB_SDRAM
 195 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
 196 /*
 197  * Base Register 2 and Option Register 2 configure SDRAM.
 198  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 199  *
 200  * For BR2, need:
 201  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 202  *    port-size = 32-bits = BR2[19:20] = 11
 203  *    no parity checking = BR2[21:22] = 00
 204  *    SDRAM for MSEL = BR2[24:26] = 011
 205  *    Valid = BR[31] = 1
 206  *
 207  * 0    4    8    12   16   20   24   28
 208  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
 209  */
 210
 211 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_LBC_SDRAM_BASE \
 212                                         | BR_PS_32 \
 213                                         | BR_MS_SDRAM \
 214                                         | BR_V)
 215                                         /* 0xF0001861 */
 216 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_LBC_SDRAM_BASE
 217 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_64MB)
 218
 219 /*
 220  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 221  *
 222  * For OR2, need:
 223  *    64MB mask for AM, OR2[0:7] = 1111 1100
 224  *                 XAM, OR2[17:18] = 11
 225  *    9 columns OR2[19-21] = 010
 226  *    13 rows   OR2[23-25] = 100
 227  *    EAD set for extra time OR[31] = 1
 228  *
 229  * 0    4    8    12   16   20   24   28
 230  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
 231  */
 232
 233 #define CONFIG_SYS_OR2_PRELIM   (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
 234                         | OR_SDRAM_XAM \
 235                         | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
 236                         | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
 237                         | OR_SDRAM_EAD)
 238                         /* 0xFC006901 */
 239
 240                                 /* LB sdram refresh timer, about 6us */
 241 #define CONFIG_SYS_LBC_LSRT     0x32000000
 242                                 /* LB refresh timer prescal, 266MHz/32 */
 243 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 244
 245 #define CONFIG_SYS_LBC_LSDMR_COMMON     (LSDMR_RFEN \
 246                                         | LSDMR_BSMA1516 \
 247                                         | LSDMR_RFCR8 \
 248                                         | LSDMR_PRETOACT6 \
 249                                         | LSDMR_ACTTORW3 \
 250                                         | LSDMR_BL8 \
 251                                         | LSDMR_WRC3 \
 252                                         | LSDMR_CL3)
 253
 254 /*
 255  * SDRAM Controller configuration sequence.
 256  */
 257 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 258 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 259 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 260 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 261 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 262 #endif
 263
 264 /*
 265  * Serial Port
 266  */
 267 #define CONFIG_CONS_INDEX     1
 268 #define CONFIG_SYS_NS16550_SERIAL
 269 #define CONFIG_SYS_NS16550_REG_SIZE    1
 270 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 271
 272 #define CONFIG_SYS_BAUDRATE_TABLE  \
 273                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 274
 275 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 276 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 277
 278 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 279 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
 280
 281 /* I2C */
 282 #define CONFIG_SYS_I2C
 283 #define CONFIG_SYS_I2C_FSL
 284 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 285 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 286 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 287 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 288 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 289 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 290 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69}, {1, 0x69} }
 291 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
 292
 293 /* TSEC */
 294 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 295 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 296 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 297 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 298
 299 /*
 300  * General PCI
 301  * Addresses are mapped 1-1.
 302  */
 303 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 304 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 305 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 306 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 307 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 308 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 309 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 310 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 311 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 312
 313 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 314 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 315 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 316 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 317 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 318 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 319 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 320 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 321 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 322
 323 #if defined(CONFIG_PCI)
 324
 325 #define PCI_64BIT
 326 #define PCI_ONE_PCI1
 327 #if defined(PCI_64BIT)
 328 #undef PCI_ALL_PCI1
 329 #undef PCI_TWO_PCI1
 330 #undef PCI_ONE_PCI1
 331 #endif
 332
 333 #undef CONFIG_EEPRO100
 334 #undef CONFIG_TULIP
 335
 336 #if !defined(CONFIG_PCI_PNP)
 337         #define PCI_ENET0_IOADDR        0xFIXME
 338         #define PCI_ENET0_MEMADDR       0xFIXME
 339         #define PCI_IDSEL_NUMBER        0xFIXME
 340 #endif
 341
 342 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 343 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 344
 345 #endif  /* CONFIG_PCI */
 346
 347 /*
 348  * TSEC configuration
 349  */
 350 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
 351
 352 #if defined(CONFIG_TSEC_ENET)
 353
 354 #define CONFIG_TSEC1    1
 355 #define CONFIG_TSEC1_NAME       "TSEC0"
 356 #define CONFIG_TSEC2    1
 357 #define CONFIG_TSEC2_NAME       "TSEC1"
 358 #define CONFIG_PHY_BCM5421S     1
 359 #define TSEC1_PHY_ADDR          0x19
 360 #define TSEC2_PHY_ADDR          0x1a
 361 #define TSEC1_PHYIDX            0
 362 #define TSEC2_PHYIDX            0
 363 #define TSEC1_FLAGS             TSEC_GIGABIT
 364 #define TSEC2_FLAGS             TSEC_GIGABIT
 365
 366 /* Options are: TSEC[0-1] */
 367 #define CONFIG_ETHPRIME         "TSEC0"
 368
 369 #endif  /* CONFIG_TSEC_ENET */
 370
 371 /*
 372  * Environment
 373  */
 374 #ifndef CONFIG_SYS_RAMBOOT
 375         #define CONFIG_ENV_IS_IN_FLASH  1
 376         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 377         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 378         #define CONFIG_ENV_SIZE         0x2000
 379
 380 /* Address and size of Redundant Environment Sector     */
 381 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 382 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 383
 384 #else
 385         #define CONFIG_SYS_NO_FLASH     1       /* Flash is not usable now */
 386         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 387         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 388         #define CONFIG_ENV_SIZE         0x2000
 389 #endif
 390
 391 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 392 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 393
 394 /*
 395  * BOOTP options
 396  */
 397 #define CONFIG_BOOTP_BOOTFILESIZE
 398 #define CONFIG_BOOTP_BOOTPATH
 399 #define CONFIG_BOOTP_GATEWAY
 400 #define CONFIG_BOOTP_HOSTNAME
 401
 402 /*
 403  * Command line configuration.
 404  */
 405
 406 #if defined(CONFIG_PCI)
 407     #define CONFIG_CMD_PCI
 408 #endif
 409
 410 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 411
 412 /*
 413  * Miscellaneous configurable options
 414  */
 415 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 416 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 417
 418 #if defined(CONFIG_CMD_KGDB)
 419         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 420 #else
 421         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 422 #endif
 423
 424                                 /* Print Buffer Size */
 425 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 426 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 427                                 /* Boot Argument Buffer Size */
 428 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 429
 430 /*
 431  * For booting Linux, the board info and command line data
 432  * have to be in the first 256 MB of memory, since this is
 433  * the maximum mapped by the Linux kernel during initialization.
 434  */
 435                                 /* Initial Memory map for Linux*/
 436 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 437
 438 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 439
 440 #if 1 /*528/264*/
 441 #define CONFIG_SYS_HRCW_LOW (\
 442         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 443         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 444         HRCWL_CSB_TO_CLKIN |\
 445         HRCWL_VCO_1X2 |\
 446         HRCWL_CORE_TO_CSB_2X1)
 447 #elif 0 /*396/132*/
 448 #define CONFIG_SYS_HRCW_LOW (\
 449         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 450         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 451         HRCWL_CSB_TO_CLKIN |\
 452         HRCWL_VCO_1X4 |\
 453         HRCWL_CORE_TO_CSB_3X1)
 454 #elif 0 /*264/132*/
 455 #define CONFIG_SYS_HRCW_LOW (\
 456         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 457         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 458         HRCWL_CSB_TO_CLKIN |\
 459         HRCWL_VCO_1X4 |\
 460         HRCWL_CORE_TO_CSB_2X1)
 461 #elif 0 /*132/132*/
 462 #define CONFIG_SYS_HRCW_LOW (\
 463         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 464         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 465         HRCWL_CSB_TO_CLKIN |\
 466         HRCWL_VCO_1X4 |\
 467         HRCWL_CORE_TO_CSB_1X1)
 468 #elif 0 /*264/264 */
 469 #define CONFIG_SYS_HRCW_LOW (\
 470         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 471         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 472         HRCWL_CSB_TO_CLKIN |\
 473         HRCWL_VCO_1X4 |\
 474         HRCWL_CORE_TO_CSB_1X1)
 475 #endif
 476
 477 #if defined(PCI_64BIT)
 478 #define CONFIG_SYS_HRCW_HIGH (\
 479         HRCWH_PCI_HOST |\
 480         HRCWH_64_BIT_PCI |\
 481         HRCWH_PCI1_ARBITER_ENABLE |\
 482         HRCWH_PCI2_ARBITER_DISABLE |\
 483         HRCWH_CORE_ENABLE |\
 484         HRCWH_FROM_0X00000100 |\
 485         HRCWH_BOOTSEQ_DISABLE |\
 486         HRCWH_SW_WATCHDOG_DISABLE |\
 487         HRCWH_ROM_LOC_LOCAL_16BIT |\
 488         HRCWH_TSEC1M_IN_GMII |\
 489         HRCWH_TSEC2M_IN_GMII)
 490 #else
 491 #define CONFIG_SYS_HRCW_HIGH (\
 492         HRCWH_PCI_HOST |\
 493         HRCWH_32_BIT_PCI |\
 494         HRCWH_PCI1_ARBITER_ENABLE |\
 495         HRCWH_PCI2_ARBITER_ENABLE |\
 496         HRCWH_CORE_ENABLE |\
 497         HRCWH_FROM_0X00000100 |\
 498         HRCWH_BOOTSEQ_DISABLE |\
 499         HRCWH_SW_WATCHDOG_DISABLE |\
 500         HRCWH_ROM_LOC_LOCAL_16BIT |\
 501         HRCWH_TSEC1M_IN_GMII |\
 502         HRCWH_TSEC2M_IN_GMII)
 503 #endif
 504
 505 /* System IO Config */
 506 #define CONFIG_SYS_SICRH 0
 507 #define CONFIG_SYS_SICRL SICRL_LDP_A
 508
 509 #define CONFIG_SYS_HID0_INIT    0x000000000
 510 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
 511                                 | HID0_ENABLE_INSTRUCTION_CACHE)
 512
 513 /* #define CONFIG_SYS_HID0_FINAL        (\
 514         HID0_ENABLE_INSTRUCTION_CACHE |\
 515         HID0_ENABLE_M_BIT |\
 516         HID0_ENABLE_ADDRESS_BROADCAST) */
 517
 518 #define CONFIG_SYS_HID2 HID2_HBE
 519
 520 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 521
 522 /* DDR @ 0x00000000 */
 523 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 524                                 | BATL_PP_RW \
 525                                 | BATL_MEMCOHERENCE)
 526 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 527                                 | BATU_BL_256M \
 528                                 | BATU_VS \
 529                                 | BATU_VP)
 530
 531 /* PCI @ 0x80000000 */
 532 #ifdef CONFIG_PCI
 533 #define CONFIG_PCI_INDIRECT_BRIDGE
 534 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE \
 535                                 | BATL_PP_RW \
 536                                 | BATL_MEMCOHERENCE)
 537 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 538                                 | BATU_BL_256M \
 539                                 | BATU_VS \
 540                                 | BATU_VP)
 541 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 542                                 | BATL_PP_RW \
 543                                 | BATL_CACHEINHIBIT \
 544                                 | BATL_GUARDEDSTORAGE)
 545 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 546                                 | BATU_BL_256M \
 547                                 | BATU_VS \
 548                                 | BATU_VP)
 549 #else
 550 #define CONFIG_SYS_IBAT1L       (0)
 551 #define CONFIG_SYS_IBAT1U       (0)
 552 #define CONFIG_SYS_IBAT2L       (0)
 553 #define CONFIG_SYS_IBAT2U       (0)
 554 #endif
 555
 556 #ifdef CONFIG_MPC83XX_PCI2
 557 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE \
 558                                 | BATL_PP_RW \
 559                                 | BATL_MEMCOHERENCE)
 560 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE \
 561                                 | BATU_BL_256M \
 562                                 | BATU_VS \
 563                                 | BATU_VP)
 564 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE \
 565                                 | BATL_PP_RW \
 566                                 | BATL_CACHEINHIBIT \
 567                                 | BATL_GUARDEDSTORAGE)
 568 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE \
 569                                 | BATU_BL_256M \
 570                                 | BATU_VS \
 571                                 | BATU_VP)
 572 #else
 573 #define CONFIG_SYS_IBAT3L       (0)
 574 #define CONFIG_SYS_IBAT3U       (0)
 575 #define CONFIG_SYS_IBAT4L       (0)
 576 #define CONFIG_SYS_IBAT4U       (0)
 577 #endif
 578
 579 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
 580 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 581                                 | BATL_PP_RW \
 582                                 | BATL_CACHEINHIBIT \
 583                                 | BATL_GUARDEDSTORAGE)
 584 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 585                                 | BATU_BL_256M \
 586                                 | BATU_VS \
 587                                 | BATU_VP)
 588
 589 /* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 590 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_LBC_SDRAM_BASE \
 591                                 | BATL_PP_RW \
 592                                 | BATL_MEMCOHERENCE \
 593                                 | BATL_GUARDEDSTORAGE)
 594 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_LBC_SDRAM_BASE \
 595                                 | BATU_BL_256M \
 596                                 | BATU_VS \
 597                                 | BATU_VP)
 598
 599 #define CONFIG_SYS_IBAT7L       (0)
 600 #define CONFIG_SYS_IBAT7U       (0)
 601
 602 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 603 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 604 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 605 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 606 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 607 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 608 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 609 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 610 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 611 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 612 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 613 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 614 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 615 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 616 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 617 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 618
 619 #if defined(CONFIG_CMD_KGDB)
 620 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 621 #endif
 622
 623 /*
 624  * Environment Configuration
 625  */
 626 #define CONFIG_ENV_OVERWRITE
 627
 628 #if defined(CONFIG_TSEC_ENET)
 629 #define CONFIG_HAS_ETH0
 630 #define CONFIG_HAS_ETH1
 631 #endif
 632
 633 #define CONFIG_HOSTNAME         SBC8349
 634 #define CONFIG_ROOTPATH         "/tftpboot/rootfs"
 635 #define CONFIG_BOOTFILE         "uImage"
 636
 637                                 /* default location for tftp and bootm */
 638 #define CONFIG_LOADADDR         800000
 639
 640 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 641
 642 #define CONFIG_BAUDRATE  115200
 643
 644 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 645         "netdev=eth0\0"                                                 \
 646         "hostname=sbc8349\0"                                            \
 647         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 648                 "nfsroot=${serverip}:${rootpath}\0"                     \
 649         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 650         "addip=setenv bootargs ${bootargs} "                            \
 651                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 652                 ":${hostname}:${netdev}:off panic=1\0"                  \
 653         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 654         "flash_nfs=run nfsargs addip addtty;"                           \
 655                 "bootm ${kernel_addr}\0"                                \
 656         "flash_self=run ramargs addip addtty;"                          \
 657                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 658         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 659                 "bootm\0"                                               \
 660         "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0"               \
 661         "update=protect off ff800000 ff83ffff; "                        \
 662                 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
 663         "upd=run load update\0"                                         \
 664         "fdtaddr=780000\0"                                              \
 665         "fdtfile=sbc8349.dtb\0"                                         \
 666         ""
 667
 668 #define CONFIG_NFSBOOTCOMMAND                                           \
 669         "setenv bootargs root=/dev/nfs rw "                             \
 670                 "nfsroot=$serverip:$rootpath "                          \
 671                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 672                                                         "$netdev:off "  \
 673                 "console=$consoledev,$baudrate $othbootargs;"           \
 674         "tftp $loadaddr $bootfile;"                                     \
 675         "tftp $fdtaddr $fdtfile;"                                       \
 676         "bootm $loadaddr - $fdtaddr"
 677
 678 #define CONFIG_RAMBOOTCOMMAND                                           \
 679         "setenv bootargs root=/dev/ram rw "                             \
 680                 "console=$consoledev,$baudrate $othbootargs;"           \
 681         "tftp $ramdiskaddr $ramdiskfile;"                               \
 682         "tftp $loadaddr $bootfile;"                                     \
 683         "tftp $fdtaddr $fdtfile;"                                       \
 684         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 685
 686 #define CONFIG_BOOTCOMMAND      "run flash_self"
 687
 688 #endif  /* __CONFIG_H */