include/configs/sbc8349.h

   1 /*
   2  * WindRiver SBC8349 U-Boot configuration file.
   3  * Copyright (c) 2006, 2007 Wind River Systems, Inc.
   4  *
   5  * Paul Gortmaker <paul.gortmaker@windriver.com>
   6  * Based on the MPC8349EMDS config.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /*
  12  * sbc8349 board configuration file.
  13  */
  14
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 /*
  19  * High Level Configuration Options
  20  */
  21 #define CONFIG_E300             1       /* E300 Family */
  22 #define CONFIG_MPC83xx          1       /* MPC83xx family */
  23 #define CONFIG_MPC834x          1       /* MPC834x family */
  24 #define CONFIG_MPC8349          1       /* MPC8349 specific */
  25 #define CONFIG_SBC8349          1       /* WRS SBC8349 board specific */
  26
  27 #define CONFIG_SYS_TEXT_BASE    0xFF800000
  28
  29 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
  30 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
  31
  32 /*
  33  * The default if PCI isn't enabled, or if no PCI clk setting is given
  34  * is 66MHz; this is what the board defaults to when the PCI slot is
  35  * physically empty.  The board will automatically (i.e w/o jumpers)
  36  * clock down to 33MHz if you insert a 33MHz PCI card.
  37  */
  38 #ifdef CONFIG_PCI_33M
  39 #define CONFIG_83XX_CLKIN       33000000        /* in Hz */
  40 #else   /* 66M */
  41 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  42 #endif
  43
  44 #ifndef CONFIG_SYS_CLK_FREQ
  45 #ifdef CONFIG_PCI_33M
  46 #define CONFIG_SYS_CLK_FREQ     33000000
  47 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_8X1
  48 #else   /* 66M */
  49 #define CONFIG_SYS_CLK_FREQ     66000000
  50 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_4X1
  51 #endif
  52 #endif
  53
  54 #undef CONFIG_BOARD_EARLY_INIT_F                /* call board_pre_init */
  55
  56 #define CONFIG_SYS_IMMR         0xE0000000
  57
  58 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  59 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  60 #define CONFIG_SYS_MEMTEST_END          0x00100000
  61
  62 /*
  63  * DDR Setup
  64  */
  65 #undef CONFIG_DDR_ECC                   /* only for ECC DDR module */
  66 #undef CONFIG_DDR_ECC_CMD               /* use DDR ECC user commands */
  67 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  68 #define CONFIG_SYS_83XX_DDR_USES_CS0    /* WRS; Fsl board uses CS2/CS3 */
  69
  70 /*
  71  * 32-bit data path mode.
  72  *
  73  * Please note that using this mode for devices with the real density of 64-bit
  74  * effectively reduces the amount of available memory due to the effect of
  75  * wrapping around while translating address to row/columns, for example in the
  76  * 256MB module the upper 128MB get aliased with contents of the lower
  77  * 128MB); normally this define should be used for devices with real 32-bit
  78  * data path.
  79  */
  80 #undef CONFIG_DDR_32BIT
  81
  82 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
  83 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  84 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  85 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  86                                 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  87 #define CONFIG_DDR_2T_TIMING
  88
  89 #if defined(CONFIG_SPD_EEPROM)
  90 /*
  91  * Determine DDR configuration from I2C interface.
  92  */
  93 #define SPD_EEPROM_ADDRESS      0x52            /* DDR DIMM */
  94
  95 #else
  96 /*
  97  * Manually set up DDR parameters
  98  * NB: manual DDR setup untested on sbc834x
  99  */
 100 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
 101 #define CONFIG_SYS_DDR_CS2_CONFIG       (CSCONFIG_EN \
 102                                         | CSCONFIG_ROW_BIT_13 \
 103                                         | CSCONFIG_COL_BIT_10)
 104 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
 105 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
 106 #define CONFIG_SYS_DDR_CONTROL  0xc2000000      /* unbuffered,no DYN_PWR */
 107 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
 108
 109 #if defined(CONFIG_DDR_32BIT)
 110 /* set burst length to 8 for 32-bit data path */
 111                                 /* DLL,normal,seq,4/2.5, 8 burst len */
 112 #define CONFIG_SYS_DDR_MODE     0x00000023
 113 #else
 114 /* the default burst length is 4 - for 64-bit data path */
 115                                 /* DLL,normal,seq,4/2.5, 4 burst len */
 116 #define CONFIG_SYS_DDR_MODE     0x00000022
 117 #endif
 118 #endif
 119
 120 /*
 121  * SDRAM on the Local Bus
 122  */
 123 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* Localbus SDRAM */
 124 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 125
 126 /*
 127  * FLASH on the Local Bus
 128  */
 129 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 130 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 131 #define CONFIG_SYS_FLASH_BASE           0xFF800000      /* start of FLASH   */
 132 #define CONFIG_SYS_FLASH_SIZE           8               /* flash size in MB */
 133 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 134
 135 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE \
 136                                         | BR_PS_16      /* 16 bit port */ \
 137                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 138                                         | BR_V)         /* valid */
 139
 140 #define CONFIG_SYS_OR0_PRELIM           (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 141                                         | OR_GPCM_XAM \
 142                                         | OR_GPCM_CSNT \
 143                                         | OR_GPCM_ACS_DIV2 \
 144                                         | OR_GPCM_XACS \
 145                                         | OR_GPCM_SCY_15 \
 146                                         | OR_GPCM_TRLX_SET \
 147                                         | OR_GPCM_EHTR_SET \
 148                                         | OR_GPCM_EAD)
 149                                         /* 0xFF806FF7 */
 150
 151                                         /* window base at flash base */
 152 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 153 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 154
 155 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 156 #define CONFIG_SYS_MAX_FLASH_SECT       64      /* sectors per device */
 157
 158 #undef CONFIG_SYS_FLASH_CHECKSUM
 159 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 160 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 161
 162 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 163
 164 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 165 #define CONFIG_SYS_RAMBOOT
 166 #else
 167 #undef  CONFIG_SYS_RAMBOOT
 168 #endif
 169
 170 #define CONFIG_SYS_INIT_RAM_LOCK        1
 171                                         /* Initial RAM address */
 172 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000
 173                                         /* Size of used area in RAM*/
 174 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000
 175
 176 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 177                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 178 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 179
 180 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024)    /* Reserve 256 kB for Mon */
 181 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 182
 183 /*
 184  * Local Bus LCRR and LBCR regs
 185  *    LCRR:  DLL bypass, Clock divider is 4
 186  * External Local Bus rate is
 187  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 188  */
 189 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 190 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 191 #define CONFIG_SYS_LBC_LBCR     0x00000000
 192
 193 #undef CONFIG_SYS_LB_SDRAM      /* if board has SDRAM on local bus */
 194
 195 #ifdef CONFIG_SYS_LB_SDRAM
 196 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
 197 /*
 198  * Base Register 2 and Option Register 2 configure SDRAM.
 199  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 200  *
 201  * For BR2, need:
 202  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 203  *    port-size = 32-bits = BR2[19:20] = 11
 204  *    no parity checking = BR2[21:22] = 00
 205  *    SDRAM for MSEL = BR2[24:26] = 011
 206  *    Valid = BR[31] = 1
 207  *
 208  * 0    4    8    12   16   20   24   28
 209  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
 210  */
 211
 212 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_LBC_SDRAM_BASE \
 213                                         | BR_PS_32 \
 214                                         | BR_MS_SDRAM \
 215                                         | BR_V)
 216                                         /* 0xF0001861 */
 217 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_LBC_SDRAM_BASE
 218 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_64MB)
 219
 220 /*
 221  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 222  *
 223  * For OR2, need:
 224  *    64MB mask for AM, OR2[0:7] = 1111 1100
 225  *                 XAM, OR2[17:18] = 11
 226  *    9 columns OR2[19-21] = 010
 227  *    13 rows   OR2[23-25] = 100
 228  *    EAD set for extra time OR[31] = 1
 229  *
 230  * 0    4    8    12   16   20   24   28
 231  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
 232  */
 233
 234 #define CONFIG_SYS_OR2_PRELIM   (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
 235                         | OR_SDRAM_XAM \
 236                         | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
 237                         | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
 238                         | OR_SDRAM_EAD)
 239                         /* 0xFC006901 */
 240
 241                                 /* LB sdram refresh timer, about 6us */
 242 #define CONFIG_SYS_LBC_LSRT     0x32000000
 243                                 /* LB refresh timer prescal, 266MHz/32 */
 244 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 245
 246 #define CONFIG_SYS_LBC_LSDMR_COMMON     (LSDMR_RFEN \
 247                                         | LSDMR_BSMA1516 \
 248                                         | LSDMR_RFCR8 \
 249                                         | LSDMR_PRETOACT6 \
 250                                         | LSDMR_ACTTORW3 \
 251                                         | LSDMR_BL8 \
 252                                         | LSDMR_WRC3 \
 253                                         | LSDMR_CL3)
 254
 255 /*
 256  * SDRAM Controller configuration sequence.
 257  */
 258 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 259 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 260 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 261 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 262 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 263 #endif
 264
 265 /*
 266  * Serial Port
 267  */
 268 #define CONFIG_CONS_INDEX     1
 269 #define CONFIG_SYS_NS16550
 270 #define CONFIG_SYS_NS16550_SERIAL
 271 #define CONFIG_SYS_NS16550_REG_SIZE    1
 272 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 273
 274 #define CONFIG_SYS_BAUDRATE_TABLE  \
 275                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 276
 277 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 278 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 279
 280 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 281 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
 282 /* Use the HUSH parser */
 283 #define CONFIG_SYS_HUSH_PARSER
 284
 285 /* pass open firmware flat tree */
 286 #define CONFIG_OF_LIBFDT        1
 287 #define CONFIG_OF_BOARD_SETUP   1
 288 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 289
 290 /* I2C */
 291 #define CONFIG_SYS_I2C
 292 #define CONFIG_SYS_I2C_FSL
 293 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 294 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 295 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 296 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 297 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 298 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 299 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69}, {1, 0x69} }
 300 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
 301
 302 /* TSEC */
 303 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 304 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 305 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 306 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 307
 308 /*
 309  * General PCI
 310  * Addresses are mapped 1-1.
 311  */
 312 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 313 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 314 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 315 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 316 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 317 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 318 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 319 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 320 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 321
 322 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 323 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 324 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 325 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 326 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 327 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 328 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 329 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 330 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 331
 332 #if defined(CONFIG_PCI)
 333
 334 #define PCI_64BIT
 335 #define PCI_ONE_PCI1
 336 #if defined(PCI_64BIT)
 337 #undef PCI_ALL_PCI1
 338 #undef PCI_TWO_PCI1
 339 #undef PCI_ONE_PCI1
 340 #endif
 341
 342 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 343
 344 #undef CONFIG_EEPRO100
 345 #undef CONFIG_TULIP
 346
 347 #if !defined(CONFIG_PCI_PNP)
 348         #define PCI_ENET0_IOADDR        0xFIXME
 349         #define PCI_ENET0_MEMADDR       0xFIXME
 350         #define PCI_IDSEL_NUMBER        0xFIXME
 351 #endif
 352
 353 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 354 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 355
 356 #endif  /* CONFIG_PCI */
 357
 358 /*
 359  * TSEC configuration
 360  */
 361 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
 362
 363 #if defined(CONFIG_TSEC_ENET)
 364
 365 #define CONFIG_TSEC1    1
 366 #define CONFIG_TSEC1_NAME       "TSEC0"
 367 #define CONFIG_TSEC2    1
 368 #define CONFIG_TSEC2_NAME       "TSEC1"
 369 #define CONFIG_PHY_BCM5421S     1
 370 #define TSEC1_PHY_ADDR          0x19
 371 #define TSEC2_PHY_ADDR          0x1a
 372 #define TSEC1_PHYIDX            0
 373 #define TSEC2_PHYIDX            0
 374 #define TSEC1_FLAGS             TSEC_GIGABIT
 375 #define TSEC2_FLAGS             TSEC_GIGABIT
 376
 377 /* Options are: TSEC[0-1] */
 378 #define CONFIG_ETHPRIME         "TSEC0"
 379
 380 #endif  /* CONFIG_TSEC_ENET */
 381
 382 /*
 383  * Environment
 384  */
 385 #ifndef CONFIG_SYS_RAMBOOT
 386         #define CONFIG_ENV_IS_IN_FLASH  1
 387         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 388         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 389         #define CONFIG_ENV_SIZE         0x2000
 390
 391 /* Address and size of Redundant Environment Sector     */
 392 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 393 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 394
 395 #else
 396         #define CONFIG_SYS_NO_FLASH     1       /* Flash is not usable now */
 397         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 398         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 399         #define CONFIG_ENV_SIZE         0x2000
 400 #endif
 401
 402 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 403 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 404
 405
 406 /*
 407  * BOOTP options
 408  */
 409 #define CONFIG_BOOTP_BOOTFILESIZE
 410 #define CONFIG_BOOTP_BOOTPATH
 411 #define CONFIG_BOOTP_GATEWAY
 412 #define CONFIG_BOOTP_HOSTNAME
 413
 414
 415 /*
 416  * Command line configuration.
 417  */
 418 #include <config_cmd_default.h>
 419
 420 #define CONFIG_CMD_I2C
 421 #define CONFIG_CMD_MII
 422 #define CONFIG_CMD_PING
 423
 424 #if defined(CONFIG_PCI)
 425     #define CONFIG_CMD_PCI
 426 #endif
 427
 428 #if defined(CONFIG_SYS_RAMBOOT)
 429     #undef CONFIG_CMD_SAVEENV
 430     #undef CONFIG_CMD_LOADS
 431 #endif
 432
 433
 434 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 435
 436 /*
 437  * Miscellaneous configurable options
 438  */
 439 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 440 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 441
 442 #if defined(CONFIG_CMD_KGDB)
 443         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 444 #else
 445         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 446 #endif
 447
 448                                 /* Print Buffer Size */
 449 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 450 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 451                                 /* Boot Argument Buffer Size */
 452 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 453
 454 /*
 455  * For booting Linux, the board info and command line data
 456  * have to be in the first 256 MB of memory, since this is
 457  * the maximum mapped by the Linux kernel during initialization.
 458  */
 459                                 /* Initial Memory map for Linux*/
 460 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 461
 462 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 463
 464 #if 1 /*528/264*/
 465 #define CONFIG_SYS_HRCW_LOW (\
 466         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 467         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 468         HRCWL_CSB_TO_CLKIN |\
 469         HRCWL_VCO_1X2 |\
 470         HRCWL_CORE_TO_CSB_2X1)
 471 #elif 0 /*396/132*/
 472 #define CONFIG_SYS_HRCW_LOW (\
 473         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 474         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 475         HRCWL_CSB_TO_CLKIN |\
 476         HRCWL_VCO_1X4 |\
 477         HRCWL_CORE_TO_CSB_3X1)
 478 #elif 0 /*264/132*/
 479 #define CONFIG_SYS_HRCW_LOW (\
 480         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 481         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 482         HRCWL_CSB_TO_CLKIN |\
 483         HRCWL_VCO_1X4 |\
 484         HRCWL_CORE_TO_CSB_2X1)
 485 #elif 0 /*132/132*/
 486 #define CONFIG_SYS_HRCW_LOW (\
 487         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 488         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 489         HRCWL_CSB_TO_CLKIN |\
 490         HRCWL_VCO_1X4 |\
 491         HRCWL_CORE_TO_CSB_1X1)
 492 #elif 0 /*264/264 */
 493 #define CONFIG_SYS_HRCW_LOW (\
 494         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 495         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 496         HRCWL_CSB_TO_CLKIN |\
 497         HRCWL_VCO_1X4 |\
 498         HRCWL_CORE_TO_CSB_1X1)
 499 #endif
 500
 501 #if defined(PCI_64BIT)
 502 #define CONFIG_SYS_HRCW_HIGH (\
 503         HRCWH_PCI_HOST |\
 504         HRCWH_64_BIT_PCI |\
 505         HRCWH_PCI1_ARBITER_ENABLE |\
 506         HRCWH_PCI2_ARBITER_DISABLE |\
 507         HRCWH_CORE_ENABLE |\
 508         HRCWH_FROM_0X00000100 |\
 509         HRCWH_BOOTSEQ_DISABLE |\
 510         HRCWH_SW_WATCHDOG_DISABLE |\
 511         HRCWH_ROM_LOC_LOCAL_16BIT |\
 512         HRCWH_TSEC1M_IN_GMII |\
 513         HRCWH_TSEC2M_IN_GMII)
 514 #else
 515 #define CONFIG_SYS_HRCW_HIGH (\
 516         HRCWH_PCI_HOST |\
 517         HRCWH_32_BIT_PCI |\
 518         HRCWH_PCI1_ARBITER_ENABLE |\
 519         HRCWH_PCI2_ARBITER_ENABLE |\
 520         HRCWH_CORE_ENABLE |\
 521         HRCWH_FROM_0X00000100 |\
 522         HRCWH_BOOTSEQ_DISABLE |\
 523         HRCWH_SW_WATCHDOG_DISABLE |\
 524         HRCWH_ROM_LOC_LOCAL_16BIT |\
 525         HRCWH_TSEC1M_IN_GMII |\
 526         HRCWH_TSEC2M_IN_GMII)
 527 #endif
 528
 529 /* System IO Config */
 530 #define CONFIG_SYS_SICRH 0
 531 #define CONFIG_SYS_SICRL SICRL_LDP_A
 532
 533 #define CONFIG_SYS_HID0_INIT    0x000000000
 534 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
 535                                 | HID0_ENABLE_INSTRUCTION_CACHE)
 536
 537 /* #define CONFIG_SYS_HID0_FINAL        (\
 538         HID0_ENABLE_INSTRUCTION_CACHE |\
 539         HID0_ENABLE_M_BIT |\
 540         HID0_ENABLE_ADDRESS_BROADCAST) */
 541
 542
 543 #define CONFIG_SYS_HID2 HID2_HBE
 544
 545 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 546
 547 /* DDR @ 0x00000000 */
 548 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 549                                 | BATL_PP_RW \
 550                                 | BATL_MEMCOHERENCE)
 551 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 552                                 | BATU_BL_256M \
 553                                 | BATU_VS \
 554                                 | BATU_VP)
 555
 556 /* PCI @ 0x80000000 */
 557 #ifdef CONFIG_PCI
 558 #define CONFIG_PCI_INDIRECT_BRIDGE
 559 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE \
 560                                 | BATL_PP_RW \
 561                                 | BATL_MEMCOHERENCE)
 562 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 563                                 | BATU_BL_256M \
 564                                 | BATU_VS \
 565                                 | BATU_VP)
 566 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 567                                 | BATL_PP_RW \
 568                                 | BATL_CACHEINHIBIT \
 569                                 | BATL_GUARDEDSTORAGE)
 570 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 571                                 | BATU_BL_256M \
 572                                 | BATU_VS \
 573                                 | BATU_VP)
 574 #else
 575 #define CONFIG_SYS_IBAT1L       (0)
 576 #define CONFIG_SYS_IBAT1U       (0)
 577 #define CONFIG_SYS_IBAT2L       (0)
 578 #define CONFIG_SYS_IBAT2U       (0)
 579 #endif
 580
 581 #ifdef CONFIG_MPC83XX_PCI2
 582 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE \
 583                                 | BATL_PP_RW \
 584                                 | BATL_MEMCOHERENCE)
 585 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE \
 586                                 | BATU_BL_256M \
 587                                 | BATU_VS \
 588                                 | BATU_VP)
 589 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE \
 590                                 | BATL_PP_RW \
 591                                 | BATL_CACHEINHIBIT \
 592                                 | BATL_GUARDEDSTORAGE)
 593 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE \
 594                                 | BATU_BL_256M \
 595                                 | BATU_VS \
 596                                 | BATU_VP)
 597 #else
 598 #define CONFIG_SYS_IBAT3L       (0)
 599 #define CONFIG_SYS_IBAT3U       (0)
 600 #define CONFIG_SYS_IBAT4L       (0)
 601 #define CONFIG_SYS_IBAT4U       (0)
 602 #endif
 603
 604 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
 605 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 606                                 | BATL_PP_RW \
 607                                 | BATL_CACHEINHIBIT \
 608                                 | BATL_GUARDEDSTORAGE)
 609 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 610                                 | BATU_BL_256M \
 611                                 | BATU_VS \
 612                                 | BATU_VP)
 613
 614 /* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 615 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_LBC_SDRAM_BASE \
 616                                 | BATL_PP_RW \
 617                                 | BATL_MEMCOHERENCE \
 618                                 | BATL_GUARDEDSTORAGE)
 619 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_LBC_SDRAM_BASE \
 620                                 | BATU_BL_256M \
 621                                 | BATU_VS \
 622                                 | BATU_VP)
 623
 624 #define CONFIG_SYS_IBAT7L       (0)
 625 #define CONFIG_SYS_IBAT7U       (0)
 626
 627 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 628 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 629 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 630 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 631 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 632 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 633 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 634 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 635 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 636 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 637 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 638 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 639 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 640 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 641 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 642 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 643
 644 #if defined(CONFIG_CMD_KGDB)
 645 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 646 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 647 #endif
 648
 649 /*
 650  * Environment Configuration
 651  */
 652 #define CONFIG_ENV_OVERWRITE
 653
 654 #if defined(CONFIG_TSEC_ENET)
 655 #define CONFIG_HAS_ETH0
 656 #define CONFIG_HAS_ETH1
 657 #endif
 658
 659 #define CONFIG_HOSTNAME         SBC8349
 660 #define CONFIG_ROOTPATH         "/tftpboot/rootfs"
 661 #define CONFIG_BOOTFILE         "uImage"
 662
 663                                 /* default location for tftp and bootm */
 664 #define CONFIG_LOADADDR         800000
 665
 666 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
 667 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 668
 669 #define CONFIG_BAUDRATE  115200
 670
 671 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 672         "netdev=eth0\0"                                                 \
 673         "hostname=sbc8349\0"                                            \
 674         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 675                 "nfsroot=${serverip}:${rootpath}\0"                     \
 676         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 677         "addip=setenv bootargs ${bootargs} "                            \
 678                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 679                 ":${hostname}:${netdev}:off panic=1\0"                  \
 680         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 681         "flash_nfs=run nfsargs addip addtty;"                           \
 682                 "bootm ${kernel_addr}\0"                                \
 683         "flash_self=run ramargs addip addtty;"                          \
 684                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 685         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 686                 "bootm\0"                                               \
 687         "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0"               \
 688         "update=protect off ff800000 ff83ffff; "                        \
 689                 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
 690         "upd=run load update\0"                                         \
 691         "fdtaddr=780000\0"                                              \
 692         "fdtfile=sbc8349.dtb\0"                                         \
 693         ""
 694
 695 #define CONFIG_NFSBOOTCOMMAND                                           \
 696         "setenv bootargs root=/dev/nfs rw "                             \
 697                 "nfsroot=$serverip:$rootpath "                          \
 698                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 699                                                         "$netdev:off "  \
 700                 "console=$consoledev,$baudrate $othbootargs;"           \
 701         "tftp $loadaddr $bootfile;"                                     \
 702         "tftp $fdtaddr $fdtfile;"                                       \
 703         "bootm $loadaddr - $fdtaddr"
 704
 705 #define CONFIG_RAMBOOTCOMMAND                                           \
 706         "setenv bootargs root=/dev/ram rw "                             \
 707                 "console=$consoledev,$baudrate $othbootargs;"           \
 708         "tftp $ramdiskaddr $ramdiskfile;"                               \
 709         "tftp $loadaddr $bootfile;"                                     \
 710         "tftp $fdtaddr $fdtfile;"                                       \
 711         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 712
 713 #define CONFIG_BOOTCOMMAND      "run flash_self"
 714
 715 #endif  /* __CONFIG_H */