include/configs/sbc8349.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * WindRiver SBC8349 U-Boot configuration file.
   4  * Copyright (c) 2006, 2007 Wind River Systems, Inc.
   5  *
   6  * Paul Gortmaker <paul.gortmaker@windriver.com>
   7  * Based on the MPC8349EMDS config.
   8  */
   9
  10 /*
  11  * sbc8349 board configuration file.
  12  */
  13
  14 #ifndef __CONFIG_H
  15 #define __CONFIG_H
  16
  17 /*
  18  * High Level Configuration Options
  19  */
  20 #define CONFIG_E300             1       /* E300 Family */
  21
  22 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
  23 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
  24
  25 /*
  26  * The default if PCI isn't enabled, or if no PCI clk setting is given
  27  * is 66MHz; this is what the board defaults to when the PCI slot is
  28  * physically empty.  The board will automatically (i.e w/o jumpers)
  29  * clock down to 33MHz if you insert a 33MHz PCI card.
  30  */
  31 #ifdef CONFIG_PCI_33M
  32 #define CONFIG_83XX_CLKIN       33000000        /* in Hz */
  33 #else   /* 66M */
  34 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  35 #endif
  36
  37 #ifndef CONFIG_SYS_CLK_FREQ
  38 #ifdef CONFIG_PCI_33M
  39 #define CONFIG_SYS_CLK_FREQ     33000000
  40 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_8X1
  41 #else   /* 66M */
  42 #define CONFIG_SYS_CLK_FREQ     66000000
  43 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_4X1
  44 #endif
  45 #endif
  46
  47 #define CONFIG_SYS_IMMR         0xE0000000
  48
  49 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  50 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  51 #define CONFIG_SYS_MEMTEST_END          0x00100000
  52
  53 /*
  54  * DDR Setup
  55  */
  56 #undef CONFIG_DDR_ECC                   /* only for ECC DDR module */
  57 #undef CONFIG_DDR_ECC_CMD               /* use DDR ECC user commands */
  58 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  59 #define CONFIG_SYS_83XX_DDR_USES_CS0    /* WRS; Fsl board uses CS2/CS3 */
  60
  61 /*
  62  * 32-bit data path mode.
  63  *
  64  * Please note that using this mode for devices with the real density of 64-bit
  65  * effectively reduces the amount of available memory due to the effect of
  66  * wrapping around while translating address to row/columns, for example in the
  67  * 256MB module the upper 128MB get aliased with contents of the lower
  68  * 128MB); normally this define should be used for devices with real 32-bit
  69  * data path.
  70  */
  71 #undef CONFIG_DDR_32BIT
  72
  73 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
  74 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  75 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  76 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  77                                 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  78 #define CONFIG_DDR_2T_TIMING
  79
  80 #if defined(CONFIG_SPD_EEPROM)
  81 /*
  82  * Determine DDR configuration from I2C interface.
  83  */
  84 #define SPD_EEPROM_ADDRESS      0x52            /* DDR DIMM */
  85
  86 #else
  87 /*
  88  * Manually set up DDR parameters
  89  * NB: manual DDR setup untested on sbc834x
  90  */
  91 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
  92 #define CONFIG_SYS_DDR_CS2_CONFIG       (CSCONFIG_EN \
  93                                         | CSCONFIG_ROW_BIT_13 \
  94                                         | CSCONFIG_COL_BIT_10)
  95 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
  96 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
  97 #define CONFIG_SYS_DDR_CONTROL  0xc2000000      /* unbuffered,no DYN_PWR */
  98 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
  99
 100 #if defined(CONFIG_DDR_32BIT)
 101 /* set burst length to 8 for 32-bit data path */
 102                                 /* DLL,normal,seq,4/2.5, 8 burst len */
 103 #define CONFIG_SYS_DDR_MODE     0x00000023
 104 #else
 105 /* the default burst length is 4 - for 64-bit data path */
 106                                 /* DLL,normal,seq,4/2.5, 4 burst len */
 107 #define CONFIG_SYS_DDR_MODE     0x00000022
 108 #endif
 109 #endif
 110
 111 /*
 112  * SDRAM on the Local Bus
 113  */
 114 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* Localbus SDRAM */
 115 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 116
 117 /*
 118  * FLASH on the Local Bus
 119  */
 120 #define CONFIG_SYS_FLASH_BASE           0xFF800000      /* start of FLASH   */
 121 #define CONFIG_SYS_FLASH_SIZE           8               /* flash size in MB */
 122
 123 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE \
 124                                         | BR_PS_16      /* 16 bit port */ \
 125                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 126                                         | BR_V)         /* valid */
 127
 128 #define CONFIG_SYS_OR0_PRELIM           (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 129                                         | OR_GPCM_XAM \
 130                                         | OR_GPCM_CSNT \
 131                                         | OR_GPCM_ACS_DIV2 \
 132                                         | OR_GPCM_XACS \
 133                                         | OR_GPCM_SCY_15 \
 134                                         | OR_GPCM_TRLX_SET \
 135                                         | OR_GPCM_EHTR_SET \
 136                                         | OR_GPCM_EAD)
 137                                         /* 0xFF806FF7 */
 138
 139                                         /* window base at flash base */
 140 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 141 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 142
 143 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 144 #define CONFIG_SYS_MAX_FLASH_SECT       64      /* sectors per device */
 145
 146 #undef CONFIG_SYS_FLASH_CHECKSUM
 147 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 148 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 149
 150 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 151
 152 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 153 #define CONFIG_SYS_RAMBOOT
 154 #else
 155 #undef  CONFIG_SYS_RAMBOOT
 156 #endif
 157
 158 #define CONFIG_SYS_INIT_RAM_LOCK        1
 159                                         /* Initial RAM address */
 160 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000
 161                                         /* Size of used area in RAM*/
 162 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000
 163
 164 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 165                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 166 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 167
 168 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024)    /* Reserve 256 kB for Mon */
 169 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 170
 171 /*
 172  * Local Bus LCRR and LBCR regs
 173  *    LCRR:  DLL bypass, Clock divider is 4
 174  * External Local Bus rate is
 175  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 176  */
 177 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 178 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 179 #define CONFIG_SYS_LBC_LBCR     0x00000000
 180
 181 #undef CONFIG_SYS_LB_SDRAM      /* if board has SDRAM on local bus */
 182
 183 #ifdef CONFIG_SYS_LB_SDRAM
 184 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
 185 /*
 186  * Base Register 2 and Option Register 2 configure SDRAM.
 187  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 188  *
 189  * For BR2, need:
 190  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 191  *    port-size = 32-bits = BR2[19:20] = 11
 192  *    no parity checking = BR2[21:22] = 00
 193  *    SDRAM for MSEL = BR2[24:26] = 011
 194  *    Valid = BR[31] = 1
 195  *
 196  * 0    4    8    12   16   20   24   28
 197  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
 198  */
 199
 200 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_LBC_SDRAM_BASE \
 201                                         | BR_PS_32 \
 202                                         | BR_MS_SDRAM \
 203                                         | BR_V)
 204                                         /* 0xF0001861 */
 205 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_LBC_SDRAM_BASE
 206 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_64MB)
 207
 208 /*
 209  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 210  *
 211  * For OR2, need:
 212  *    64MB mask for AM, OR2[0:7] = 1111 1100
 213  *                 XAM, OR2[17:18] = 11
 214  *    9 columns OR2[19-21] = 010
 215  *    13 rows   OR2[23-25] = 100
 216  *    EAD set for extra time OR[31] = 1
 217  *
 218  * 0    4    8    12   16   20   24   28
 219  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
 220  */
 221
 222 #define CONFIG_SYS_OR2_PRELIM   (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
 223                         | OR_SDRAM_XAM \
 224                         | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
 225                         | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
 226                         | OR_SDRAM_EAD)
 227                         /* 0xFC006901 */
 228
 229                                 /* LB sdram refresh timer, about 6us */
 230 #define CONFIG_SYS_LBC_LSRT     0x32000000
 231                                 /* LB refresh timer prescal, 266MHz/32 */
 232 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 233
 234 #define CONFIG_SYS_LBC_LSDMR_COMMON     (LSDMR_RFEN \
 235                                         | LSDMR_BSMA1516 \
 236                                         | LSDMR_RFCR8 \
 237                                         | LSDMR_PRETOACT6 \
 238                                         | LSDMR_ACTTORW3 \
 239                                         | LSDMR_BL8 \
 240                                         | LSDMR_WRC3 \
 241                                         | LSDMR_CL3)
 242
 243 /*
 244  * SDRAM Controller configuration sequence.
 245  */
 246 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 247 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 248 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 249 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 250 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 251 #endif
 252
 253 /*
 254  * Serial Port
 255  */
 256 #define CONFIG_SYS_NS16550_SERIAL
 257 #define CONFIG_SYS_NS16550_REG_SIZE    1
 258 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 259
 260 #define CONFIG_SYS_BAUDRATE_TABLE  \
 261                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 262
 263 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 264 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 265
 266 /* I2C */
 267 #define CONFIG_SYS_I2C
 268 #define CONFIG_SYS_I2C_FSL
 269 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 270 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 271 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 272 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 273 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 274 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 275 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69}, {1, 0x69} }
 276 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
 277
 278 /* TSEC */
 279 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 280 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 281 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 282 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 283
 284 /*
 285  * General PCI
 286  * Addresses are mapped 1-1.
 287  */
 288 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 289 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 290 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 291 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 292 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 293 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 294 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 295 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 296 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 297
 298 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 299 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 300 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 301 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 302 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 303 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 304 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 305 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 306 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 307
 308 #if defined(CONFIG_PCI)
 309
 310 #define PCI_64BIT
 311 #define PCI_ONE_PCI1
 312 #if defined(PCI_64BIT)
 313 #undef PCI_ALL_PCI1
 314 #undef PCI_TWO_PCI1
 315 #undef PCI_ONE_PCI1
 316 #endif
 317
 318 #undef CONFIG_EEPRO100
 319 #undef CONFIG_TULIP
 320
 321 #if !defined(CONFIG_PCI_PNP)
 322         #define PCI_ENET0_IOADDR        0xFIXME
 323         #define PCI_ENET0_MEMADDR       0xFIXME
 324         #define PCI_IDSEL_NUMBER        0xFIXME
 325 #endif
 326
 327 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 328 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 329
 330 #endif  /* CONFIG_PCI */
 331
 332 /*
 333  * TSEC configuration
 334  */
 335
 336 #if defined(CONFIG_TSEC_ENET)
 337
 338 #define CONFIG_TSEC1    1
 339 #define CONFIG_TSEC1_NAME       "TSEC0"
 340 #define CONFIG_TSEC2    1
 341 #define CONFIG_TSEC2_NAME       "TSEC1"
 342 #define CONFIG_PHY_BCM5421S     1
 343 #define TSEC1_PHY_ADDR          0x19
 344 #define TSEC2_PHY_ADDR          0x1a
 345 #define TSEC1_PHYIDX            0
 346 #define TSEC2_PHYIDX            0
 347 #define TSEC1_FLAGS             TSEC_GIGABIT
 348 #define TSEC2_FLAGS             TSEC_GIGABIT
 349
 350 /* Options are: TSEC[0-1] */
 351 #define CONFIG_ETHPRIME         "TSEC0"
 352
 353 #endif  /* CONFIG_TSEC_ENET */
 354
 355 /*
 356  * Environment
 357  */
 358 #ifndef CONFIG_SYS_RAMBOOT
 359         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 360         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 361         #define CONFIG_ENV_SIZE         0x2000
 362
 363 /* Address and size of Redundant Environment Sector     */
 364 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 365 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 366
 367 #else
 368         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 369         #define CONFIG_ENV_SIZE         0x2000
 370 #endif
 371
 372 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 373 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 374
 375 /*
 376  * BOOTP options
 377  */
 378 #define CONFIG_BOOTP_BOOTFILESIZE
 379
 380 /*
 381  * Command line configuration.
 382  */
 383
 384 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 385
 386 /*
 387  * Miscellaneous configurable options
 388  */
 389 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 390
 391 /*
 392  * For booting Linux, the board info and command line data
 393  * have to be in the first 256 MB of memory, since this is
 394  * the maximum mapped by the Linux kernel during initialization.
 395  */
 396                                 /* Initial Memory map for Linux*/
 397 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 398
 399 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 400
 401 #if 1 /*528/264*/
 402 #define CONFIG_SYS_HRCW_LOW (\
 403         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 404         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 405         HRCWL_CSB_TO_CLKIN |\
 406         HRCWL_VCO_1X2 |\
 407         HRCWL_CORE_TO_CSB_2X1)
 408 #elif 0 /*396/132*/
 409 #define CONFIG_SYS_HRCW_LOW (\
 410         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 411         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 412         HRCWL_CSB_TO_CLKIN |\
 413         HRCWL_VCO_1X4 |\
 414         HRCWL_CORE_TO_CSB_3X1)
 415 #elif 0 /*264/132*/
 416 #define CONFIG_SYS_HRCW_LOW (\
 417         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 418         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 419         HRCWL_CSB_TO_CLKIN |\
 420         HRCWL_VCO_1X4 |\
 421         HRCWL_CORE_TO_CSB_2X1)
 422 #elif 0 /*132/132*/
 423 #define CONFIG_SYS_HRCW_LOW (\
 424         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 425         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 426         HRCWL_CSB_TO_CLKIN |\
 427         HRCWL_VCO_1X4 |\
 428         HRCWL_CORE_TO_CSB_1X1)
 429 #elif 0 /*264/264 */
 430 #define CONFIG_SYS_HRCW_LOW (\
 431         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 432         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 433         HRCWL_CSB_TO_CLKIN |\
 434         HRCWL_VCO_1X4 |\
 435         HRCWL_CORE_TO_CSB_1X1)
 436 #endif
 437
 438 #if defined(PCI_64BIT)
 439 #define CONFIG_SYS_HRCW_HIGH (\
 440         HRCWH_PCI_HOST |\
 441         HRCWH_64_BIT_PCI |\
 442         HRCWH_PCI1_ARBITER_ENABLE |\
 443         HRCWH_PCI2_ARBITER_DISABLE |\
 444         HRCWH_CORE_ENABLE |\
 445         HRCWH_FROM_0X00000100 |\
 446         HRCWH_BOOTSEQ_DISABLE |\
 447         HRCWH_SW_WATCHDOG_DISABLE |\
 448         HRCWH_ROM_LOC_LOCAL_16BIT |\
 449         HRCWH_TSEC1M_IN_GMII |\
 450         HRCWH_TSEC2M_IN_GMII)
 451 #else
 452 #define CONFIG_SYS_HRCW_HIGH (\
 453         HRCWH_PCI_HOST |\
 454         HRCWH_32_BIT_PCI |\
 455         HRCWH_PCI1_ARBITER_ENABLE |\
 456         HRCWH_PCI2_ARBITER_ENABLE |\
 457         HRCWH_CORE_ENABLE |\
 458         HRCWH_FROM_0X00000100 |\
 459         HRCWH_BOOTSEQ_DISABLE |\
 460         HRCWH_SW_WATCHDOG_DISABLE |\
 461         HRCWH_ROM_LOC_LOCAL_16BIT |\
 462         HRCWH_TSEC1M_IN_GMII |\
 463         HRCWH_TSEC2M_IN_GMII)
 464 #endif
 465
 466 /* System IO Config */
 467 #define CONFIG_SYS_SICRH 0
 468 #define CONFIG_SYS_SICRL SICRL_LDP_A
 469
 470 #define CONFIG_SYS_HID0_INIT    0x000000000
 471 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
 472                                 | HID0_ENABLE_INSTRUCTION_CACHE)
 473
 474 /* #define CONFIG_SYS_HID0_FINAL        (\
 475         HID0_ENABLE_INSTRUCTION_CACHE |\
 476         HID0_ENABLE_M_BIT |\
 477         HID0_ENABLE_ADDRESS_BROADCAST) */
 478
 479 #define CONFIG_SYS_HID2 HID2_HBE
 480
 481 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 482
 483 /* DDR @ 0x00000000 */
 484 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 485                                 | BATL_PP_RW \
 486                                 | BATL_MEMCOHERENCE)
 487 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 488                                 | BATU_BL_256M \
 489                                 | BATU_VS \
 490                                 | BATU_VP)
 491
 492 /* PCI @ 0x80000000 */
 493 #ifdef CONFIG_PCI
 494 #define CONFIG_PCI_INDIRECT_BRIDGE
 495 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE \
 496                                 | BATL_PP_RW \
 497                                 | BATL_MEMCOHERENCE)
 498 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 499                                 | BATU_BL_256M \
 500                                 | BATU_VS \
 501                                 | BATU_VP)
 502 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 503                                 | BATL_PP_RW \
 504                                 | BATL_CACHEINHIBIT \
 505                                 | BATL_GUARDEDSTORAGE)
 506 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 507                                 | BATU_BL_256M \
 508                                 | BATU_VS \
 509                                 | BATU_VP)
 510 #else
 511 #define CONFIG_SYS_IBAT1L       (0)
 512 #define CONFIG_SYS_IBAT1U       (0)
 513 #define CONFIG_SYS_IBAT2L       (0)
 514 #define CONFIG_SYS_IBAT2U       (0)
 515 #endif
 516
 517 #ifdef CONFIG_MPC83XX_PCI2
 518 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE \
 519                                 | BATL_PP_RW \
 520                                 | BATL_MEMCOHERENCE)
 521 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE \
 522                                 | BATU_BL_256M \
 523                                 | BATU_VS \
 524                                 | BATU_VP)
 525 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE \
 526                                 | BATL_PP_RW \
 527                                 | BATL_CACHEINHIBIT \
 528                                 | BATL_GUARDEDSTORAGE)
 529 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE \
 530                                 | BATU_BL_256M \
 531                                 | BATU_VS \
 532                                 | BATU_VP)
 533 #else
 534 #define CONFIG_SYS_IBAT3L       (0)
 535 #define CONFIG_SYS_IBAT3U       (0)
 536 #define CONFIG_SYS_IBAT4L       (0)
 537 #define CONFIG_SYS_IBAT4U       (0)
 538 #endif
 539
 540 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
 541 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 542                                 | BATL_PP_RW \
 543                                 | BATL_CACHEINHIBIT \
 544                                 | BATL_GUARDEDSTORAGE)
 545 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 546                                 | BATU_BL_256M \
 547                                 | BATU_VS \
 548                                 | BATU_VP)
 549
 550 /* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 551 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_LBC_SDRAM_BASE \
 552                                 | BATL_PP_RW \
 553                                 | BATL_MEMCOHERENCE \
 554                                 | BATL_GUARDEDSTORAGE)
 555 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_LBC_SDRAM_BASE \
 556                                 | BATU_BL_256M \
 557                                 | BATU_VS \
 558                                 | BATU_VP)
 559
 560 #define CONFIG_SYS_IBAT7L       (0)
 561 #define CONFIG_SYS_IBAT7U       (0)
 562
 563 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 564 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 565 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 566 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 567 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 568 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 569 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 570 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 571 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 572 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 573 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 574 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 575 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 576 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 577 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 578 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 579
 580 #if defined(CONFIG_CMD_KGDB)
 581 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 582 #endif
 583
 584 /*
 585  * Environment Configuration
 586  */
 587 #define CONFIG_ENV_OVERWRITE
 588
 589 #if defined(CONFIG_TSEC_ENET)
 590 #define CONFIG_HAS_ETH0
 591 #define CONFIG_HAS_ETH1
 592 #endif
 593
 594 #define CONFIG_HOSTNAME         "SBC8349"
 595 #define CONFIG_ROOTPATH         "/tftpboot/rootfs"
 596 #define CONFIG_BOOTFILE         "uImage"
 597
 598                                 /* default location for tftp and bootm */
 599 #define CONFIG_LOADADDR         800000
 600
 601 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 602         "netdev=eth0\0"                                                 \
 603         "hostname=sbc8349\0"                                            \
 604         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 605                 "nfsroot=${serverip}:${rootpath}\0"                     \
 606         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 607         "addip=setenv bootargs ${bootargs} "                            \
 608                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 609                 ":${hostname}:${netdev}:off panic=1\0"                  \
 610         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 611         "flash_nfs=run nfsargs addip addtty;"                           \
 612                 "bootm ${kernel_addr}\0"                                \
 613         "flash_self=run ramargs addip addtty;"                          \
 614                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 615         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 616                 "bootm\0"                                               \
 617         "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0"               \
 618         "update=protect off ff800000 ff83ffff; "                        \
 619                 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
 620         "upd=run load update\0"                                         \
 621         "fdtaddr=780000\0"                                              \
 622         "fdtfile=sbc8349.dtb\0"                                         \
 623         ""
 624
 625 #define CONFIG_NFSBOOTCOMMAND                                           \
 626         "setenv bootargs root=/dev/nfs rw "                             \
 627                 "nfsroot=$serverip:$rootpath "                          \
 628                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 629                                                         "$netdev:off "  \
 630                 "console=$consoledev,$baudrate $othbootargs;"           \
 631         "tftp $loadaddr $bootfile;"                                     \
 632         "tftp $fdtaddr $fdtfile;"                                       \
 633         "bootm $loadaddr - $fdtaddr"
 634
 635 #define CONFIG_RAMBOOTCOMMAND                                           \
 636         "setenv bootargs root=/dev/ram rw "                             \
 637                 "console=$consoledev,$baudrate $othbootargs;"           \
 638         "tftp $ramdiskaddr $ramdiskfile;"                               \
 639         "tftp $loadaddr $bootfile;"                                     \
 640         "tftp $fdtaddr $fdtfile;"                                       \
 641         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 642
 643 #define CONFIG_BOOTCOMMAND      "run flash_self"
 644
 645 #endif  /* __CONFIG_H */