1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * WindRiver SBC8349 U-Boot configuration file.
4 * Copyright (c) 2006, 2007 Wind River Systems, Inc.
6 * Paul Gortmaker <paul.gortmaker@windriver.com>
7 * Based on the MPC8349EMDS config.
11 * sbc8349 board configuration file.
18 * High Level Configuration Options
20 #define CONFIG_E300 1 /* E300 Family */
22 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
23 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
26 * The default if PCI isn't enabled, or if no PCI clk setting is given
27 * is 66MHz; this is what the board defaults to when the PCI slot is
28 * physically empty. The board will automatically (i.e w/o jumpers)
29 * clock down to 33MHz if you insert a 33MHz PCI card.
32 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */
34 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
37 #ifndef CONFIG_SYS_CLK_FREQ
39 #define CONFIG_SYS_CLK_FREQ 33000000
40 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
42 #define CONFIG_SYS_CLK_FREQ 66000000
43 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
47 #define CONFIG_SYS_IMMR 0xE0000000
49 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
50 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
51 #define CONFIG_SYS_MEMTEST_END 0x00100000
56 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
57 #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
58 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
59 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */
62 * 32-bit data path mode.
64 * Please note that using this mode for devices with the real density of 64-bit
65 * effectively reduces the amount of available memory due to the effect of
66 * wrapping around while translating address to row/columns, for example in the
67 * 256MB module the upper 128MB get aliased with contents of the lower
68 * 128MB); normally this define should be used for devices with real 32-bit
71 #undef CONFIG_DDR_32BIT
73 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
74 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
75 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
76 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
77 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
78 #define CONFIG_DDR_2T_TIMING
80 #if defined(CONFIG_SPD_EEPROM)
82 * Determine DDR configuration from I2C interface.
84 #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */
88 * Manually set up DDR parameters
89 * NB: manual DDR setup untested on sbc834x
91 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
92 #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
93 | CSCONFIG_ROW_BIT_13 \
94 | CSCONFIG_COL_BIT_10)
95 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
96 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
97 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
98 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
100 #if defined(CONFIG_DDR_32BIT)
101 /* set burst length to 8 for 32-bit data path */
102 /* DLL,normal,seq,4/2.5, 8 burst len */
103 #define CONFIG_SYS_DDR_MODE 0x00000023
105 /* the default burst length is 4 - for 64-bit data path */
106 /* DLL,normal,seq,4/2.5, 4 burst len */
107 #define CONFIG_SYS_DDR_MODE 0x00000022
112 * SDRAM on the Local Bus
114 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
115 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
118 * FLASH on the Local Bus
120 #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
121 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
123 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
124 | BR_PS_16 /* 16 bit port */ \
125 | BR_MS_GPCM /* MSEL = GPCM */ \
128 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
139 /* window base at flash base */
140 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
141 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
143 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
144 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
146 #undef CONFIG_SYS_FLASH_CHECKSUM
147 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
148 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
150 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
152 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
153 #define CONFIG_SYS_RAMBOOT
155 #undef CONFIG_SYS_RAMBOOT
158 #define CONFIG_SYS_INIT_RAM_LOCK 1
159 /* Initial RAM address */
160 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
161 /* Size of used area in RAM*/
162 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
164 #define CONFIG_SYS_GBL_DATA_OFFSET \
165 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
166 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
168 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
169 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
172 * Local Bus LCRR and LBCR regs
173 * LCRR: DLL bypass, Clock divider is 4
174 * External Local Bus rate is
175 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
177 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
178 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
179 #define CONFIG_SYS_LBC_LBCR 0x00000000
181 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
183 #ifdef CONFIG_SYS_LB_SDRAM
184 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
186 * Base Register 2 and Option Register 2 configure SDRAM.
187 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
190 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
191 * port-size = 32-bits = BR2[19:20] = 11
192 * no parity checking = BR2[21:22] = 00
193 * SDRAM for MSEL = BR2[24:26] = 011
196 * 0 4 8 12 16 20 24 28
197 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
200 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
205 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
206 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
209 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
212 * 64MB mask for AM, OR2[0:7] = 1111 1100
213 * XAM, OR2[17:18] = 11
214 * 9 columns OR2[19-21] = 010
215 * 13 rows OR2[23-25] = 100
216 * EAD set for extra time OR[31] = 1
218 * 0 4 8 12 16 20 24 28
219 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
222 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
224 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
225 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
229 /* LB sdram refresh timer, about 6us */
230 #define CONFIG_SYS_LBC_LSRT 0x32000000
231 /* LB refresh timer prescal, 266MHz/32 */
232 #define CONFIG_SYS_LBC_MRTPR 0x20000000
234 #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
244 * SDRAM Controller configuration sequence.
246 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
247 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
248 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
249 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
250 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
256 #define CONFIG_SYS_NS16550_SERIAL
257 #define CONFIG_SYS_NS16550_REG_SIZE 1
258 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
260 #define CONFIG_SYS_BAUDRATE_TABLE \
261 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
263 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
264 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
267 #define CONFIG_SYS_I2C
268 #define CONFIG_SYS_I2C_FSL
269 #define CONFIG_SYS_FSL_I2C_SPEED 400000
270 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
271 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
272 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
273 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
274 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
275 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} }
276 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
279 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
280 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
281 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
282 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
286 * Addresses are mapped 1-1.
288 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
289 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
290 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
291 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
292 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
293 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
294 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
295 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
296 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
298 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
299 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
300 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
301 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
302 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
303 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
304 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
305 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
306 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
308 #if defined(CONFIG_PCI)
310 #undef CONFIG_EEPRO100
313 #if !defined(CONFIG_PCI_PNP)
314 #define PCI_ENET0_IOADDR 0xFIXME
315 #define PCI_ENET0_MEMADDR 0xFIXME
316 #define PCI_IDSEL_NUMBER 0xFIXME
319 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
320 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
322 #endif /* CONFIG_PCI */
328 #if defined(CONFIG_TSEC_ENET)
330 #define CONFIG_TSEC1 1
331 #define CONFIG_TSEC1_NAME "TSEC0"
332 #define CONFIG_TSEC2 1
333 #define CONFIG_TSEC2_NAME "TSEC1"
334 #define CONFIG_PHY_BCM5421S 1
335 #define TSEC1_PHY_ADDR 0x19
336 #define TSEC2_PHY_ADDR 0x1a
337 #define TSEC1_PHYIDX 0
338 #define TSEC2_PHYIDX 0
339 #define TSEC1_FLAGS TSEC_GIGABIT
340 #define TSEC2_FLAGS TSEC_GIGABIT
342 /* Options are: TSEC[0-1] */
343 #define CONFIG_ETHPRIME "TSEC0"
345 #endif /* CONFIG_TSEC_ENET */
350 #ifndef CONFIG_SYS_RAMBOOT
351 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
352 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
353 #define CONFIG_ENV_SIZE 0x2000
355 /* Address and size of Redundant Environment Sector */
356 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
357 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
360 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
361 #define CONFIG_ENV_SIZE 0x2000
364 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
365 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
370 #define CONFIG_BOOTP_BOOTFILESIZE
373 * Command line configuration.
376 #undef CONFIG_WATCHDOG /* watchdog disabled */
379 * Miscellaneous configurable options
381 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
384 * For booting Linux, the board info and command line data
385 * have to be in the first 256 MB of memory, since this is
386 * the maximum mapped by the Linux kernel during initialization.
388 /* Initial Memory map for Linux*/
389 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
391 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
394 #define CONFIG_SYS_HRCW_LOW (\
395 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
396 HRCWL_DDR_TO_SCB_CLK_1X1 |\
397 HRCWL_CSB_TO_CLKIN |\
399 HRCWL_CORE_TO_CSB_2X1)
401 #define CONFIG_SYS_HRCW_LOW (\
402 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
403 HRCWL_DDR_TO_SCB_CLK_1X1 |\
404 HRCWL_CSB_TO_CLKIN |\
406 HRCWL_CORE_TO_CSB_3X1)
408 #define CONFIG_SYS_HRCW_LOW (\
409 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
410 HRCWL_DDR_TO_SCB_CLK_1X1 |\
411 HRCWL_CSB_TO_CLKIN |\
413 HRCWL_CORE_TO_CSB_2X1)
415 #define CONFIG_SYS_HRCW_LOW (\
416 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
417 HRCWL_DDR_TO_SCB_CLK_1X1 |\
418 HRCWL_CSB_TO_CLKIN |\
420 HRCWL_CORE_TO_CSB_1X1)
422 #define CONFIG_SYS_HRCW_LOW (\
423 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
424 HRCWL_DDR_TO_SCB_CLK_1X1 |\
425 HRCWL_CSB_TO_CLKIN |\
427 HRCWL_CORE_TO_CSB_1X1)
430 #if defined(CONFIG_PCI_64BIT)
431 #define CONFIG_SYS_HRCW_HIGH (\
434 HRCWH_PCI1_ARBITER_ENABLE |\
435 HRCWH_PCI2_ARBITER_DISABLE |\
437 HRCWH_FROM_0X00000100 |\
438 HRCWH_BOOTSEQ_DISABLE |\
439 HRCWH_SW_WATCHDOG_DISABLE |\
440 HRCWH_ROM_LOC_LOCAL_16BIT |\
441 HRCWH_TSEC1M_IN_GMII |\
442 HRCWH_TSEC2M_IN_GMII)
444 #define CONFIG_SYS_HRCW_HIGH (\
447 HRCWH_PCI1_ARBITER_ENABLE |\
448 HRCWH_PCI2_ARBITER_ENABLE |\
450 HRCWH_FROM_0X00000100 |\
451 HRCWH_BOOTSEQ_DISABLE |\
452 HRCWH_SW_WATCHDOG_DISABLE |\
453 HRCWH_ROM_LOC_LOCAL_16BIT |\
454 HRCWH_TSEC1M_IN_GMII |\
455 HRCWH_TSEC2M_IN_GMII)
458 /* System IO Config */
459 #define CONFIG_SYS_SICRH 0
460 #define CONFIG_SYS_SICRL SICRL_LDP_A
462 #define CONFIG_SYS_HID0_INIT 0x000000000
463 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
464 | HID0_ENABLE_INSTRUCTION_CACHE)
466 /* #define CONFIG_SYS_HID0_FINAL (\
467 HID0_ENABLE_INSTRUCTION_CACHE |\
469 HID0_ENABLE_ADDRESS_BROADCAST) */
471 #define CONFIG_SYS_HID2 HID2_HBE
473 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
475 /* DDR @ 0x00000000 */
476 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
479 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
484 /* PCI @ 0x80000000 */
486 #define CONFIG_PCI_INDIRECT_BRIDGE
487 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
490 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
494 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
496 | BATL_CACHEINHIBIT \
497 | BATL_GUARDEDSTORAGE)
498 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
503 #define CONFIG_SYS_IBAT1L (0)
504 #define CONFIG_SYS_IBAT1U (0)
505 #define CONFIG_SYS_IBAT2L (0)
506 #define CONFIG_SYS_IBAT2U (0)
509 #ifdef CONFIG_MPC83XX_PCI2
510 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
513 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
517 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
519 | BATL_CACHEINHIBIT \
520 | BATL_GUARDEDSTORAGE)
521 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
526 #define CONFIG_SYS_IBAT3L (0)
527 #define CONFIG_SYS_IBAT3U (0)
528 #define CONFIG_SYS_IBAT4L (0)
529 #define CONFIG_SYS_IBAT4U (0)
532 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
533 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
535 | BATL_CACHEINHIBIT \
536 | BATL_GUARDEDSTORAGE)
537 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
542 /* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
543 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \
545 | BATL_MEMCOHERENCE \
546 | BATL_GUARDEDSTORAGE)
547 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \
552 #define CONFIG_SYS_IBAT7L (0)
553 #define CONFIG_SYS_IBAT7U (0)
555 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
556 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
557 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
558 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
559 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
560 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
561 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
562 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
563 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
564 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
565 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
566 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
567 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
568 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
569 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
570 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
572 #if defined(CONFIG_CMD_KGDB)
573 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
577 * Environment Configuration
579 #define CONFIG_ENV_OVERWRITE
581 #if defined(CONFIG_TSEC_ENET)
582 #define CONFIG_HAS_ETH0
583 #define CONFIG_HAS_ETH1
586 #define CONFIG_HOSTNAME "SBC8349"
587 #define CONFIG_ROOTPATH "/tftpboot/rootfs"
588 #define CONFIG_BOOTFILE "uImage"
590 /* default location for tftp and bootm */
591 #define CONFIG_LOADADDR 800000
593 #define CONFIG_EXTRA_ENV_SETTINGS \
595 "hostname=sbc8349\0" \
596 "nfsargs=setenv bootargs root=/dev/nfs rw " \
597 "nfsroot=${serverip}:${rootpath}\0" \
598 "ramargs=setenv bootargs root=/dev/ram rw\0" \
599 "addip=setenv bootargs ${bootargs} " \
600 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
601 ":${hostname}:${netdev}:off panic=1\0" \
602 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
603 "flash_nfs=run nfsargs addip addtty;" \
604 "bootm ${kernel_addr}\0" \
605 "flash_self=run ramargs addip addtty;" \
606 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
607 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
609 "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \
610 "update=protect off ff800000 ff83ffff; " \
611 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
612 "upd=run load update\0" \
614 "fdtfile=sbc8349.dtb\0" \
617 #define CONFIG_NFSBOOTCOMMAND \
618 "setenv bootargs root=/dev/nfs rw " \
619 "nfsroot=$serverip:$rootpath " \
620 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
622 "console=$consoledev,$baudrate $othbootargs;" \
623 "tftp $loadaddr $bootfile;" \
624 "tftp $fdtaddr $fdtfile;" \
625 "bootm $loadaddr - $fdtaddr"
627 #define CONFIG_RAMBOOTCOMMAND \
628 "setenv bootargs root=/dev/ram rw " \
629 "console=$consoledev,$baudrate $othbootargs;" \
630 "tftp $ramdiskaddr $ramdiskfile;" \
631 "tftp $loadaddr $bootfile;" \
632 "tftp $fdtaddr $fdtfile;" \
633 "bootm $loadaddr $ramdiskaddr $fdtaddr"
635 #define CONFIG_BOOTCOMMAND "run flash_self"
637 #endif /* __CONFIG_H */