3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 * Gary Jennejohn <gj@denx.de>
6 * David Mueller <d.mueller@elsoft.ch>
8 * Modified for the friendly-arm SBC-2410X by
10 * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
12 * Configuation settings for the friendly-arm SBC-2410X board.
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 * If we are developing, we might want to start armboot from ram
38 * so we MUST NOT initialize critical regs like mem-timing ...
40 #undef CONFIG_SKIP_LOWLEVEL_INIT /* undef for developing */
43 * High Level Configuration Options
46 #define CONFIG_ARM920T 1 /* This is an ARM920T Core */
47 #define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
48 #define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */
50 /* input clock of PLL */
51 #define CONFIG_SYS_CLK_FREQ 12000000/* the SBC2410X has 12MHz input clock */
54 #define USE_920T_MMU 1
55 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
58 * Size of malloc() pool
60 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
61 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
66 #define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
67 #define CS8900_BASE 0x19000300
68 #define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
71 * select serial console configuration
73 #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SBC2410X */
75 /************************************************************
77 ************************************************************/
78 #define CONFIG_RTC_S3C24X0 1
80 /* allow to overwrite serial and ethaddr */
81 #define CONFIG_ENV_OVERWRITE
83 #define CONFIG_BAUDRATE 115200
87 * Command line configuration.
89 #include <config_cmd_default.h>
91 #define CONFIG_CMD_ASKENV
92 #define CONFIG_CMD_CACHE
93 #define CONFIG_CMD_DATE
94 #define CONFIG_CMD_DHCP
95 #define CONFIG_CMD_ELF
96 #define CONFIG_CMD_PING
97 #define CONFIG_CMD_REGINFO
100 #define CONFIG_BOOTDELAY 3
101 #define CONFIG_BOOTARGS "console=ttySAC0 root=/dev/nfs nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
102 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b
103 #define CONFIG_NETMASK 255.255.255.0
104 #define CONFIG_IPADDR 192.168.0.69
105 #define CONFIG_SERVERIP 192.168.0.1
106 /*#define CONFIG_BOOTFILE "elinos-lart" */
107 #define CONFIG_BOOTCOMMAND "dhcp; bootm"
109 #if defined(CONFIG_CMD_KGDB)
110 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
111 /* what's this ? it's not used anywhere */
112 #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
116 * Miscellaneous configurable options
118 #define CFG_LONGHELP /* undef to save memory */
119 #define CFG_PROMPT "[ ~ljh@GDLC ]# " /* Monitor Command Prompt */
120 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
121 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
122 #define CFG_MAXARGS 16 /* max number of command args */
123 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
125 #define CFG_MEMTEST_START 0x30000000 /* memtest works on */
126 #define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
128 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
130 #define CFG_LOAD_ADDR 0x33000000 /* default load address */
132 /* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
133 /* it to wrap 100 times (total 1562500) to get 1 sec. */
134 #define CFG_HZ 1562500
136 /* valid baudrates */
137 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
139 /*-----------------------------------------------------------------------
142 * The stack sizes are set up in start.S using the settings below
144 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
145 #ifdef CONFIG_USE_IRQ
146 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
147 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
150 /*-----------------------------------------------------------------------
151 * Physical Memory Map
153 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
154 #define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
155 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
157 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
159 #define CFG_FLASH_BASE PHYS_FLASH_1
161 /*-----------------------------------------------------------------------
162 * FLASH and environment organization
164 /* #define CONFIG_AMD_LV400 1 /\* uncomment this if you have a LV400 flash *\/ */
166 #define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
168 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
170 #ifdef CONFIG_AMD_LV800
171 #define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
172 #define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
173 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
176 #ifdef CONFIG_AMD_LV400
177 #define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
178 #define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
179 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */
182 /* timeout values are in ticks */
183 #define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */
184 #define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */
186 #define CFG_ENV_IS_IN_FLASH 1
187 #define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
189 /*-----------------------------------------------------------------------
190 * NAND flash settings
192 #if defined(CONFIG_CMD_NAND)
193 #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
194 #define SECTORSIZE 512
196 #define ADDR_COLUMN 1
198 #define ADDR_COLUMN_PAGE 3
200 #define NAND_ChipID_UNKNOWN 0x00
201 #define NAND_MAX_FLOORS 1
202 #define NAND_MAX_CHIPS 1
204 #define NAND_WAIT_READY(nand) NF_WaitRB()
205 #define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH)
206 #define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW)
207 #define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d)
208 #define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d)
209 #define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d)
210 #define WRITE_NAND(d, adr) NF_Write(d)
211 #define READ_NAND(adr) NF_Read()
212 /* the following functions are NOP's because S3C24X0 handles this in hardware */
213 #define NAND_CTL_CLRALE(nandptr)
214 #define NAND_CTL_SETALE(nandptr)
215 #define NAND_CTL_CLRCLE(nandptr)
216 #define NAND_CTL_SETCLE(nandptr)
217 /* #undef CONFIG_MTD_NAND_VERIFY_WRITE */
218 #endif /* CONFIG_CMD_NAND */
220 #define CONFIG_SETUP_MEMORY_TAGS
221 #define CONFIG_INITRD_TAG
222 #define CONFIG_CMDLINE_TAG
224 #define CFG_HUSH_PARSER
225 #define CFG_PROMPT_HUSH_PS2 "> "
227 #define CONFIG_CMDLINE_EDITING
229 #ifdef CONFIG_CMDLINE_EDITING
230 #undef CONFIG_AUTO_COMPLETE
232 #define CONFIG_AUTO_COMPLETE
235 #endif /* __CONFIG_H */