1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2011 The Chromium OS Authors.
11 #define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
12 #define CONFIG_TRACE_EARLY_SIZE (16 << 20)
13 #define CONFIG_TRACE_EARLY
14 #define CONFIG_TRACE_EARLY_ADDR 0x00100000
17 #ifndef CONFIG_SPL_BUILD
18 #define CONFIG_IO_TRACE
22 #define CONFIG_SYS_TIMER_RATE 1000000
27 #define CONFIG_HOST_MAX_DEVICES 4
30 * Size of malloc() pool, before and after relocation
32 #define CONFIG_MALLOC_F_ADDR 0x0010000
33 #define CONFIG_SYS_MALLOC_LEN (32 << 20) /* 32MB */
35 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
37 /* turn on command-line edit/c/auto */
39 /* SPI - enable all SPI flash types for testing purposes */
41 #define CONFIG_I2C_EDID
43 /* Memory things - we don't really want a memory test */
44 #define CONFIG_SYS_LOAD_ADDR 0x00000000
45 #define CONFIG_SYS_FDT_LOAD_ADDR 0x100
47 #define CONFIG_PHYSMEM
49 /* Size of our emulated memory */
50 #define SB_CONCAT(x, y) x ## y
51 #define SB_TO_UL(s) SB_CONCAT(s, UL)
52 #define CONFIG_SYS_SDRAM_BASE 0
53 #define CONFIG_SYS_SDRAM_SIZE \
54 (SB_TO_UL(CONFIG_SANDBOX_RAM_SIZE_MB) << 20)
55 #define CONFIG_SYS_MONITOR_BASE 0
57 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
60 #define BOOT_TARGET_DEVICES(func) \
67 #include <config_distro_bootcmd.h>
70 #define CONFIG_KEEP_SERVERADDR
71 #define CONFIG_UDP_CHECKSUM
72 #define CONFIG_TIMESTAMP
73 #define CONFIG_BOOTP_SERVERIP
75 #ifndef SANDBOX_NO_SDL
76 #define CONFIG_SANDBOX_SDL
79 /* LCD and keyboard require SDL support */
80 #ifdef CONFIG_SANDBOX_SDL
81 #define LCD_BPP LCD_COLOR16
82 #define CONFIG_LCD_BMP_RLE8
84 #define CONFIG_KEYBOARD
86 #define SANDBOX_SERIAL_SETTINGS "stdin=serial,cros-ec-keyb,usbkbd\0" \
87 "stdout=serial,vidconsole\0" \
88 "stderr=serial,vidconsole\0"
90 #define SANDBOX_SERIAL_SETTINGS "stdin=serial\0" \
91 "stdout=serial,vidconsole\0" \
92 "stderr=serial,vidconsole\0"
95 #define SANDBOX_ETH_SETTINGS "ethaddr=00:00:11:22:33:44\0" \
96 "eth3addr=00:00:11:22:33:45\0" \
97 "eth5addr=00:00:11:22:33:46\0" \
98 "eth6addr=00:00:11:22:33:47\0" \
101 #define MEM_LAYOUT_ENV_SETTINGS \
102 "bootm_size=0x10000000\0" \
103 "kernel_addr_r=0x1000000\0" \
104 "fdt_addr_r=0xc00000\0" \
105 "ramdisk_addr_r=0x2000000\0" \
106 "scriptaddr=0x1000\0" \
107 "pxefile_addr_r=0x2000\0"
109 #define CONFIG_EXTRA_ENV_SETTINGS \
110 SANDBOX_SERIAL_SETTINGS \
111 SANDBOX_ETH_SETTINGS \
113 MEM_LAYOUT_ENV_SETTINGS
115 #ifndef CONFIG_SPL_BUILD
116 #define CONFIG_SYS_IDE_MAXBUS 1
117 #define CONFIG_SYS_ATA_IDE0_OFFSET 0
118 #define CONFIG_SYS_IDE_MAXDEVICE 2
119 #define CONFIG_SYS_ATA_BASE_ADDR 0x100
120 #define CONFIG_SYS_ATA_DATA_OFFSET 0
121 #define CONFIG_SYS_ATA_REG_OFFSET 1
122 #define CONFIG_SYS_ATA_ALT_OFFSET 2
123 #define CONFIG_SYS_ATA_STRIDE 4
126 #define CONFIG_SCSI_AHCI_PLAT
127 #define CONFIG_SYS_SCSI_MAX_DEVICE 2
128 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 8
129 #define CONFIG_SYS_SCSI_MAX_LUN 4
131 #define CONFIG_SYS_SATA_MAX_DEVICE 2
133 #define CONFIG_MISC_INIT_F