include/configs/sama5d3_xplained.h

   1 /*
   2  * Configuration settings for the SAMA5D3 Xplained board.
   3  *
   4  * Copyright (C) 2014 Atmel Corporation
   5  *                    Bo Shen <voice.shen@atmel.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include "at91-sama5_common.h"
  14
  15 /*
  16  * This needs to be defined for the OHCI code to work but it is defined as
  17  * ATMEL_ID_UHPHS in the CPU specific header files.
  18  */
  19 #define ATMEL_ID_UHP                    32
  20
  21 /*
  22  * Specify the clock enable bit in the PMC_SCER register.
  23  */
  24 #define ATMEL_PMC_UHP                   (1 <<  6)
  25
  26 /* SDRAM */
  27 #define CONFIG_NR_DRAM_BANKS            1
  28 #define CONFIG_SYS_SDRAM_BASE           0x20000000
  29 #define CONFIG_SYS_SDRAM_SIZE           0x10000000
  30
  31 #ifdef CONFIG_SPL_BUILD
  32 #define CONFIG_SYS_INIT_SP_ADDR         0x318000
  33 #else
  34 #define CONFIG_SYS_INIT_SP_ADDR \
  35         (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
  36 #endif
  37
  38 /* NAND flash */
  39 #ifdef CONFIG_CMD_NAND
  40 #define CONFIG_NAND_ATMEL
  41 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  42 #define CONFIG_SYS_NAND_BASE            0x60000000
  43 /* our ALE is AD21 */
  44 #define CONFIG_SYS_NAND_MASK_ALE        (1 << 21)
  45 /* our CLE is AD22 */
  46 #define CONFIG_SYS_NAND_MASK_CLE        (1 << 22)
  47 #define CONFIG_SYS_NAND_ONFI_DETECTION
  48
  49 #define CONFIG_MTD_DEVICE
  50 #define CONFIG_MTD_PARTITIONS
  51 #endif
  52 /* PMECC & PMERRLOC */
  53 #define CONFIG_ATMEL_NAND_HWECC
  54 #define CONFIG_ATMEL_NAND_HW_PMECC
  55 #define CONFIG_PMECC_CAP                4
  56 #define CONFIG_PMECC_SECTOR_SIZE        512
  57
  58 /* USB */
  59
  60 #ifdef CONFIG_CMD_USB
  61 #define CONFIG_USB_ATMEL
  62 #define CONFIG_USB_ATMEL_CLK_SEL_UPLL
  63 #define CONFIG_USB_OHCI_NEW
  64 #define CONFIG_SYS_USB_OHCI_CPU_INIT
  65 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00600000
  66 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "SAMA5D3 Xplained"
  67 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
  68 #endif
  69
  70 #define CONFIG_SYS_LOAD_ADDR                    0x22000000 /* load address */
  71
  72 /* SPL */
  73 #define CONFIG_SPL_TEXT_BASE            0x300000
  74 #define CONFIG_SPL_MAX_SIZE             0x18000
  75 #define CONFIG_SPL_BSS_START_ADDR       0x20000000
  76 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  77 #define CONFIG_SYS_SPL_MALLOC_START     0x20080000
  78 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x80000
  79
  80 #define CONFIG_SYS_MONITOR_LEN          (512 << 10)
  81
  82 #ifdef CONFIG_SD_BOOT
  83 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
  84 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  85
  86 #elif CONFIG_NAND_BOOT
  87 #define CONFIG_SPL_NAND_DRIVERS
  88 #define CONFIG_SPL_NAND_BASE
  89 #endif
  90 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
  91 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  92 #define CONFIG_SYS_NAND_PAGE_SIZE       0x800
  93 #define CONFIG_SYS_NAND_PAGE_COUNT      64
  94 #define CONFIG_SYS_NAND_OOBSIZE         64
  95 #define CONFIG_SYS_NAND_BLOCK_SIZE      0x20000
  96 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0x0
  97 #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
  98
  99 #endif