include/configs/sama5d3_xplained.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuration settings for the SAMA5D3 Xplained board.
   4  *
   5  * Copyright (C) 2014 Atmel Corporation
   6  *                    Bo Shen <voice.shen@atmel.com>
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #include "at91-sama5_common.h"
  13
  14 /*
  15  * This needs to be defined for the OHCI code to work but it is defined as
  16  * ATMEL_ID_UHPHS in the CPU specific header files.
  17  */
  18 #define ATMEL_ID_UHP                    32
  19
  20 /*
  21  * Specify the clock enable bit in the PMC_SCER register.
  22  */
  23 #define ATMEL_PMC_UHP                   (1 <<  6)
  24
  25 /* SDRAM */
  26 #define CONFIG_NR_DRAM_BANKS            1
  27 #define CONFIG_SYS_SDRAM_BASE           0x20000000
  28 #define CONFIG_SYS_SDRAM_SIZE           0x10000000
  29
  30 #ifdef CONFIG_SPL_BUILD
  31 #define CONFIG_SYS_INIT_SP_ADDR         0x318000
  32 #else
  33 #define CONFIG_SYS_INIT_SP_ADDR \
  34         (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
  35 #endif
  36
  37 /* NAND flash */
  38 #ifdef CONFIG_CMD_NAND
  39 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  40 #define CONFIG_SYS_NAND_BASE            0x60000000
  41 /* our ALE is AD21 */
  42 #define CONFIG_SYS_NAND_MASK_ALE        (1 << 21)
  43 /* our CLE is AD22 */
  44 #define CONFIG_SYS_NAND_MASK_CLE        (1 << 22)
  45 #define CONFIG_SYS_NAND_ONFI_DETECTION
  46 #endif
  47 /* PMECC & PMERRLOC */
  48 #define CONFIG_ATMEL_NAND_HWECC
  49 #define CONFIG_ATMEL_NAND_HW_PMECC
  50 #define CONFIG_PMECC_CAP                4
  51 #define CONFIG_PMECC_SECTOR_SIZE        512
  52
  53 /* USB */
  54
  55 #ifdef CONFIG_CMD_USB
  56 #define CONFIG_USB_ATMEL
  57 #define CONFIG_USB_ATMEL_CLK_SEL_UPLL
  58 #define CONFIG_USB_OHCI_NEW
  59 #define CONFIG_SYS_USB_OHCI_CPU_INIT
  60 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00600000
  61 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "SAMA5D3 Xplained"
  62 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
  63 #endif
  64
  65 #define CONFIG_SYS_LOAD_ADDR                    0x22000000 /* load address */
  66
  67 /* SPL */
  68 #define CONFIG_SPL_TEXT_BASE            0x300000
  69 #define CONFIG_SPL_MAX_SIZE             0x18000
  70 #define CONFIG_SPL_BSS_START_ADDR       0x20000000
  71 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  72 #define CONFIG_SYS_SPL_MALLOC_START     0x20080000
  73 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x80000
  74
  75 #define CONFIG_SYS_MONITOR_LEN          (512 << 10)
  76
  77 #ifdef CONFIG_SD_BOOT
  78 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
  79 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  80
  81 #elif CONFIG_NAND_BOOT
  82 #define CONFIG_SPL_NAND_DRIVERS
  83 #define CONFIG_SPL_NAND_BASE
  84 #endif
  85 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
  86 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  87 #define CONFIG_SYS_NAND_PAGE_SIZE       0x800
  88 #define CONFIG_SYS_NAND_PAGE_COUNT      64
  89 #define CONFIG_SYS_NAND_OOBSIZE         64
  90 #define CONFIG_SYS_NAND_BLOCK_SIZE      0x20000
  91 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0x0
  92 #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
  93
  94 #endif