1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuration settings for the SAMA5D3 Xplained board.
5 * Copyright (C) 2014 Atmel Corporation
6 * Bo Shen <voice.shen@atmel.com>
12 #include "at91-sama5_common.h"
15 * This needs to be defined for the OHCI code to work but it is defined as
16 * ATMEL_ID_UHPHS in the CPU specific header files.
18 #define ATMEL_ID_UHP 32
21 * Specify the clock enable bit in the PMC_SCER register.
23 #define ATMEL_PMC_UHP (1 << 6)
26 #define CONFIG_SYS_SDRAM_BASE 0x20000000
27 #define CONFIG_SYS_SDRAM_SIZE 0x10000000
29 #ifdef CONFIG_SPL_BUILD
30 #define CONFIG_SYS_INIT_SP_ADDR 0x318000
32 #define CONFIG_SYS_INIT_SP_ADDR \
33 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
37 #ifdef CONFIG_CMD_NAND
38 #define CONFIG_SYS_MAX_NAND_DEVICE 1
39 #define CONFIG_SYS_NAND_BASE 0x60000000
41 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
43 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
44 #define CONFIG_SYS_NAND_ONFI_DETECTION
49 #define CONFIG_USB_ATMEL
50 #define CONFIG_USB_ATMEL_CLK_SEL_UPLL
51 #define CONFIG_USB_OHCI_NEW
52 #define CONFIG_SYS_USB_OHCI_CPU_INIT
53 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00600000
54 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained"
55 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
58 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
61 #define CONFIG_SPL_MAX_SIZE 0x18000
62 #define CONFIG_SPL_BSS_START_ADDR 0x20000000
63 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
64 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000
65 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
67 #define CONFIG_SYS_MONITOR_LEN (512 << 10)
70 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
71 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
73 #elif CONFIG_NAND_BOOT
74 #define CONFIG_SPL_NAND_DRIVERS
75 #define CONFIG_SPL_NAND_BASE
77 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
78 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
79 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800
80 #define CONFIG_SYS_NAND_PAGE_COUNT 64
81 #define CONFIG_SYS_NAND_OOBSIZE 64
82 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
83 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0