arm: zynq: Setup non zero SPL FIT load address
[platform/kernel/u-boot.git] / include / configs / sama5d2_ptc_ek.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Configuration file for the SAMA5D2 PTC EK Board.
4  *
5  * Copyright (C) 2017 Microchip Technology Inc.
6  *                    Wenyou Yang <wenyou.yang@microchip.com>
7  *                    Ludovic Desroches <ludovic.desroches@microchip.com>
8  */
9
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 #include "at91-sama5_common.h"
14
15 #undef CONFIG_SYS_AT91_MAIN_CLOCK
16 #define CONFIG_SYS_AT91_MAIN_CLOCK      24000000 /* from 24 MHz crystal */
17
18 /* SDRAM */
19 #define CONFIG_SYS_SDRAM_BASE           0x20000000
20 #define CONFIG_SYS_SDRAM_SIZE           0x20000000
21
22 #define CONFIG_SYS_INIT_SP_ADDR \
23         (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
24
25 #define CONFIG_SYS_LOAD_ADDR            0x22000000 /* load address */
26
27 /* NAND Flash */
28 #ifdef CONFIG_CMD_NAND
29 #define CONFIG_SYS_MAX_NAND_DEVICE      1
30 #define CONFIG_SYS_NAND_BASE            ATMEL_BASE_CS3
31 /* our ALE is AD21 */
32 #define CONFIG_SYS_NAND_MASK_ALE        BIT(21)
33 /* our CLE is AD22 */
34 #define CONFIG_SYS_NAND_MASK_CLE        BIT(22)
35 #define CONFIG_SYS_NAND_ONFI_DETECTION
36 /* PMECC & PMERRLOC */
37 #define CONFIG_ATMEL_NAND_HWECC
38 #define CONFIG_ATMEL_NAND_HW_PMECC
39 #endif
40
41 #endif /* __CONFIG_H */