3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jtm@smoothsmoothie.com>
13 * Configuration settings for the WindRiver SBC8260 board.
14 * See http://www.windriver.com/products/html/sbc8260.html
16 * See file CREDITS for list of people who contributed to this
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
38 #undef DEBUG /* General debug */
39 #undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
41 #undef CONFIG_LOGBUFFER /* External logbuffer support */
43 /*****************************************************************************
45 * These settings must match the way _your_ board is set up
47 *****************************************************************************/
49 /* What is the oscillator's (UX2) frequency in Hz? */
50 #define CONFIG_8260_CLKIN 66666600
52 /*-----------------------------------------------------------------------
53 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
54 *-----------------------------------------------------------------------
55 * What should MODCK_H be? It is dependent on the oscillator
56 * frequency, MODCK[1-3], and desired CPM and core frequencies.
57 * Here are some example values (all frequencies are in MHz):
59 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
60 * ------- ---------- --- --- ---- ----- ----- -----
61 * 0x1 0x5 33 100 133 Open Close Open
62 * 0x1 0x6 33 100 166 Open Open Close
63 * 0x1 0x7 33 100 200 Open Open Open
65 * 0x2 0x2 33 133 133 Close Open Close
66 * 0x2 0x3 33 133 166 Close Open Open
67 * 0x2 0x4 33 133 200 Open Close Close
68 * 0x2 0x5 33 133 233 Open Close Open
69 * 0x2 0x6 33 133 266 Open Open Close
71 * 0x5 0x5 66 133 133 Open Close Open
72 * 0x5 0x6 66 133 166 Open Open Close
73 * 0x5 0x7 66 133 200 Open Open Open
74 * 0x6 0x0 66 133 233 Close Close Close
75 * 0x6 0x1 66 133 266 Close Close Open
76 * 0x6 0x2 66 133 300 Close Open Close
78 #define CFG_SBC_MODCK_H 0x05
80 /* Define this if you want to boot from 0x00000100. If you don't define
81 * this, you will need to program the bootloader to 0xfff00000, and
82 * get the hardware reset config words at 0xfe000000. The simplest
83 * way to do that is to program the bootloader at both addresses.
84 * It is suggested that you just let U-Boot live at 0x00000000.
86 #define CFG_SBC_BOOT_LOW 1
88 /* What should the base address of the main FLASH be and how big is
89 * it (in MBytes)? This must contain TEXT_BASE from board/sacsng/config.mk
90 * The main FLASH is whichever is connected to *CS0.
92 #define CFG_FLASH0_BASE 0x40000000
93 #define CFG_FLASH0_SIZE 2
95 /* What should the base address of the secondary FLASH be and how big
96 * is it (in Mbytes)? The secondary FLASH is whichever is connected
99 #define CFG_FLASH1_BASE 0x60000000
100 #define CFG_FLASH1_SIZE 2
102 /* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
104 #define CONFIG_VERY_BIG_RAM 1
106 /* What should be the base address of SDRAM DIMM and how big is
107 * it (in Mbytes)? This will normally auto-configure via the SPD.
109 #define CFG_SDRAM0_BASE 0x00000000
110 #define CFG_SDRAM0_SIZE 64
113 * Memory map example with 64 MB DIMM:
115 * 0x0000 0000 Exception Vector code, 8k
118 * 0x0000 2000 Free for Application Use
124 * 0x03F5 FF30 Monitor Stack (Growing downward)
125 * Monitor Stack Buffer (0x80)
126 * 0x03F5 FFB0 Board Info Data
127 * 0x03F6 0000 Malloc Arena
128 * : CFG_ENV_SECT_SIZE, 16k
129 * : CFG_MALLOC_LEN, 128k
130 * 0x03FC 0000 RAM Copy of Monitor Code
131 * : CFG_MONITOR_LEN, 256k
132 * 0x03FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
135 #define CONFIG_POST (CFG_POST_MEMORY | \
140 * select serial console configuration
142 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
143 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
146 * if CONFIG_CONS_NONE is defined, then the serial console routines must
149 #define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
150 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
151 #undef CONFIG_CONS_NONE /* define if console on neither */
152 #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
155 * select ethernet configuration
157 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
158 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
161 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
162 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
163 * from CONFIG_COMMANDS to remove support for networking.
166 #undef CONFIG_ETHER_ON_SCC
167 #define CONFIG_ETHER_ON_FCC
168 #undef CONFIG_ETHER_NONE /* define if ethernet on neither */
170 #ifdef CONFIG_ETHER_ON_SCC
171 #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
172 #endif /* CONFIG_ETHER_ON_SCC */
174 #ifdef CONFIG_ETHER_ON_FCC
175 #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
176 #undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */
177 #define CONFIG_MII /* MII PHY management */
178 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
180 * Port pins used for bit-banged MII communictions (if applicable).
183 #define MDIO_PORT 2 /* Port A=0, B=1, C=2, D=3 */
184 #define MDIO_ACTIVE (iop->pdir |= 0x40000000)
185 #define MDIO_TRISTATE (iop->pdir &= ~0x40000000)
186 #define MDIO_READ ((iop->pdat & 0x40000000) != 0)
188 #define MDIO(bit) if(bit) iop->pdat |= 0x40000000; \
189 else iop->pdat &= ~0x40000000
191 #define MDC(bit) if(bit) iop->pdat |= 0x80000000; \
192 else iop->pdat &= ~0x80000000
194 #define MIIDELAY udelay(50)
195 #endif /* CONFIG_ETHER_ON_FCC */
197 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
203 # define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
205 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
210 * - Select bus for bd/buffers (see 28-13)
211 * - Enable Full Duplex in FSMR
213 # define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
214 # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
215 # define CFG_CPMFCR_RAMTYPE 0
216 # define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
218 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
220 #define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progress enabled */
223 * Configure for RAM tests.
225 #undef CFG_DRAM_TEST /* calls other tests in board.c */
229 * Status LED for power up status feedback.
231 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
233 #define STATUS_LED_PAR im_ioport.iop_ppara
234 #define STATUS_LED_DIR im_ioport.iop_pdira
235 #define STATUS_LED_ODR im_ioport.iop_podra
236 #define STATUS_LED_DAT im_ioport.iop_pdata
238 #define STATUS_LED_BIT 0x00000800 /* LED 0 is on PA.20 */
239 #define STATUS_LED_PERIOD (CFG_HZ)
240 #define STATUS_LED_STATE STATUS_LED_OFF
241 #define STATUS_LED_BIT1 0x00001000 /* LED 1 is on PA.19 */
242 #define STATUS_LED_PERIOD1 (CFG_HZ)
243 #define STATUS_LED_STATE1 STATUS_LED_OFF
244 #define STATUS_LED_BIT2 0x00002000 /* LED 2 is on PA.18 */
245 #define STATUS_LED_PERIOD2 (CFG_HZ/2)
246 #define STATUS_LED_STATE2 STATUS_LED_ON
248 #define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
250 #define STATUS_LED_YELLOW 0
251 #define STATUS_LED_GREEN 1
252 #define STATUS_LED_RED 2
253 #define STATUS_LED_BOOT 1
257 * Select SPI support configuration
259 #define CONFIG_SOFT_SPI /* Enable SPI driver */
260 #define MAX_SPI_BYTES 4 /* Maximum number of bytes we can handle */
261 #undef DEBUG_SPI /* Disable SPI debugging */
264 * Software (bit-bang) SPI driver configuration
266 #ifdef CONFIG_SOFT_SPI
269 * Software (bit-bang) SPI driver configuration
271 #define I2C_SCLK 0x00002000 /* PD 18: Shift clock */
272 #define I2C_MOSI 0x00004000 /* PD 17: Master Out, Slave In */
273 #define I2C_MISO 0x00008000 /* PD 16: Master In, Slave Out */
275 #undef SPI_INIT /* no port initialization needed */
276 #define SPI_READ ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0)
277 #define SPI_SDA(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \
278 else immr->im_ioport.iop_pdatd &= ~I2C_MOSI
279 #define SPI_SCL(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \
280 else immr->im_ioport.iop_pdatd &= ~I2C_SCLK
281 #define SPI_DELAY /* No delay is needed */
282 #endif /* CONFIG_SOFT_SPI */
286 * select I2C support configuration
288 * Supported configurations are {none, software, hardware} drivers.
289 * If the software driver is chosen, there are some additional
290 * configuration items that the driver uses to drive the port pins.
292 #undef CONFIG_HARD_I2C /* I2C with hardware support */
293 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
294 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
295 #define CFG_I2C_SLAVE 0x7F
298 * Software (bit-bang) I2C driver configuration
300 #ifdef CONFIG_SOFT_I2C
301 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
302 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
303 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
304 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
305 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
306 else iop->pdat &= ~0x00010000
307 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
308 else iop->pdat &= ~0x00020000
309 #define I2C_DELAY udelay(20) /* 1/4 I2C clock duration */
310 #endif /* CONFIG_SOFT_I2C */
312 /* Define this to reserve an entire FLASH sector for
313 * environment variables. Otherwise, the environment will be
314 * put in the same sector as U-Boot, and changing variables
315 * will erase U-Boot temporarily
317 #define CFG_ENV_IN_OWN_SECT 1
319 /* Define this to contain any number of null terminated strings that
320 * will be part of the default enviroment compiled into the boot image.
322 #define CONFIG_EXTRA_ENV_SETTINGS \
324 "serverip=192.168.123.205\0" \
325 "ipaddr=192.168.123.203\0" \
326 "checkhostname=VR8500\0" \
329 "tftpboot 0x140000 /bdi2000/u-boot.bin; " \
330 "protect off 60000000 6003FFFF; " \
331 "erase 60000000 6003FFFF; " \
332 "cp.b 140000 60000000 ${filesize}; " \
333 "protect on 60000000 6003FFFF\0" \
335 "protect off 60040000 6004FFFF; " \
336 "erase 60040000 6004FFFF; " \
337 "cp.b 40040000 60040000 10000; " \
338 "protect on 60040000 6004FFFF\0" \
340 "protect off 60000000 6003FFFF; " \
341 "erase 60000000 6003FFFF; " \
342 "cp.b 40000000 60000000 40000; " \
343 "protect on 60000000 6003FFFF\0" \
345 "protect off 40040000 4004FFFF; " \
346 "erase 40040000 4004FFFF; " \
347 "protect on 40040000 4004FFFF\0" \
349 "protect off 60040000 6004FFFF; " \
350 "erase 60040000 6004FFFF; " \
351 "protect on 60040000 6004FFFF\0" \
357 "setenv bootargs root=/dev/ram0 rw quiet " \
358 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
361 "root-on-initrd-debug="\
366 "setenv bootargs root=/dev/ram0 rw debug " \
367 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
368 "run debug-hook\\;" \
376 "setenv bootargs root=/dev/nfs rw quiet " \
377 "nfsroot=\\${serverip}:\\${rootpath} " \
378 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
381 "root-on-nfs-debug="\
386 "setenv bootargs root=/dev/nfs rw debug " \
387 "nfsroot=\\${serverip}:\\${rootpath} " \
388 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
389 "run debug-hook\\;" \
393 "setenv checkhostname;" \
394 "setenv ethaddr 00:09:70:00:00:01;" \
396 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} debug " \
397 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
402 "echo ipaddr ${ipaddr};" \
403 "echo serverip ${serverip};" \
404 "echo gatewayip ${gatewayip};" \
405 "echo netmask ${netmask};" \
406 "echo hostname ${hostname}\0" \
407 "ana=run adc ; run dac\0" \
408 "adc=run adc-12 ; run adc-34\0" \
409 "adc-12=echo ### ADC-12 ; imd.b e 81 e\0" \
410 "adc-34=echo ### ADC-34 ; imd.b f 81 e\0" \
411 "dac=echo ### DAC ; imd.b 11 81 5\0" \
414 /* What should the console's baud rate be? */
415 #define CONFIG_BAUDRATE 9600
417 /* Ethernet MAC address */
418 #define CONFIG_ETHADDR 00:09:70:00:00:00
420 /* The default Ethernet MAC address can be overwritten just once */
421 #ifdef CONFIG_ETHADDR
422 #define CONFIG_OVERWRITE_ETHADDR_ONCE 1
426 * Define this to do some miscellaneous board-specific initialization.
428 #define CONFIG_MISC_INIT_R
430 /* Set to a positive value to delay for running BOOTCOMMAND */
431 #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
433 /* Be selective on what keys can delay or stop the autoboot process
436 #define CONFIG_AUTOBOOT_KEYED
437 #define CONFIG_AUTOBOOT_PROMPT "Autobooting...\n"
438 #define CONFIG_AUTOBOOT_STOP_STR " "
439 #undef CONFIG_AUTOBOOT_DELAY_STR
440 #define CONFIG_ZERO_BOOTDELAY_CHECK
441 #define DEBUG_BOOTKEYS 0
443 /* Define a command string that is automatically executed when no character
444 * is read on the console interface withing "Boot Delay" after reset.
446 #undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
447 #define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
449 #ifdef CONFIG_BOOT_ROOT_INITRD
450 #define CONFIG_BOOTCOMMAND \
454 "setenv bootargs root=/dev/ram0 rw quiet " \
455 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
458 #endif /* CONFIG_BOOT_ROOT_INITRD */
460 #ifdef CONFIG_BOOT_ROOT_NFS
461 #define CONFIG_BOOTCOMMAND \
465 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} quiet " \
466 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
469 #endif /* CONFIG_BOOT_ROOT_NFS */
471 #define CONFIG_BOOTP_RANDOM_DELAY /* Randomize the BOOTP retry delay */
473 /* Add support for a few extra bootp options like:
475 * - DNS (up to 2 servers)
476 * - Send hostname to DHCP server
478 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
479 CONFIG_BOOTP_BOOTFILESIZE | \
481 CONFIG_BOOTP_DNS2 | \
482 CONFIG_BOOTP_SEND_HOSTNAME)
484 /* undef this to save memory */
487 /* Monitor Command Prompt */
488 #define CFG_PROMPT "=> "
490 #undef CFG_HUSH_PARSER
491 #ifdef CFG_HUSH_PARSER
492 #define CFG_PROMPT_HUSH_PS2 "> "
495 /* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
496 * of an image is printed by image commands like bootm or iminfo.
498 #define CONFIG_TIMESTAMP
500 /* If this variable is defined, an environment variable named "ver"
501 * is created by U-Boot showing the U-Boot version.
503 #define CONFIG_VERSION_VARIABLE
505 /* What U-Boot subsytems do you want enabled? */
506 #ifdef CONFIG_ETHER_ON_FCC
507 # define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
520 # define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
531 #endif /* CONFIG_ETHER_ON_FCC */
533 /* Where do the internal registers live? */
534 #define CFG_IMMR 0xF0000000
536 #undef CONFIG_WATCHDOG /* disable the watchdog */
538 /*****************************************************************************
540 * You should not have to modify any of the following settings
542 *****************************************************************************/
544 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
545 #define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */
546 #define CONFIG_SACSng 1 /* munged for the SACSng */
547 #define CONFIG_CPM2 1 /* Has a CPM2 */
549 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
550 #include <cmd_confdefs.h>
554 * Miscellaneous configurable options
556 #define CFG_BOOTM_HEADER_QUIET 1 /* Suppress the image header dump */
557 /* in the bootm command. */
558 #define CFG_BOOTM_PROGESS_QUIET 1 /* Suppress the progress displays, */
559 /* "## <message>" from the bootm cmd */
560 #define CFG_BOOTP_CHECK_HOSTNAME 1 /* If checkhostname environment is */
561 /* defined, then the hostname param */
562 /* validated against checkhostname. */
563 #define CFG_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up */
564 #define CFG_BOOTP_SHORT_RANDOM_DELAY 1 /* Use a short random delay value */
565 /* (limited to maximum of 1024 msec) */
566 #define CFG_CHK_FOR_ABORT_AT_LEAST_ONCE 1
567 /* Check for abort key presses */
568 /* at least once in dependent of the */
569 /* CONFIG_BOOTDELAY value. */
570 #define CFG_CONSOLE_INFO_QUIET 1 /* Don't print console @ startup */
571 #define CFG_FAULT_ECHO_LINK_DOWN 1 /* Echo the inverted Ethernet link */
572 /* state to the fault LED. */
573 #define CFG_FAULT_MII_ADDR 0x02 /* MII addr of the PHY to check for */
574 /* the Ethernet link state. */
575 #define CFG_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing */
576 /* until the TFTP is successful. */
577 #define CFG_STATUS_OFF_AFTER_NETBOOT 1 /* After a successful netboot, */
578 /* turn off the STATUS LEDs. */
579 #define CFG_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on */
581 #define CFG_TFTP_BLOCKS_PER_HASH 100 /* For every XX blocks, output a '#' */
582 /* to signify that tftp is moving. */
583 #define CFG_TFTP_HASHES_PER_FLASH 200 /* For every '#' hashes, */
584 /* flash the status LED. */
585 #define CFG_TFTP_HASHES_PER_LINE 65 /* Only output XX '#'s per line */
586 /* during the tftp file transfer. */
587 #define CFG_TFTP_PROGESS_QUIET 1 /* Suppress the progress displays */
588 /* '#'s from the tftp command. */
589 #define CFG_TFTP_STATUS_QUIET 1 /* Suppress the status displays */
590 /* issued during the tftp command. */
591 #define CFG_TFTP_TIMEOUT_COUNT 5 /* How many timeouts TFTP will allow */
592 /* before it gives up. */
594 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
595 # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
597 # define CFG_CBSIZE 256 /* Console I/O Buffer Size */
600 /* Print Buffer Size */
601 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
603 #define CFG_MAXARGS 32 /* max number of command args */
605 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
607 #define CFG_LOAD_ADDR 0x400000 /* default load address */
608 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
610 #define CFG_ALT_MEMTEST /* Select full-featured memory test */
611 #define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */
612 /* the exception vector table */
613 /* to the end of the DRAM */
614 /* less monitor and malloc area */
615 #define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
616 #define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \
618 + CFG_ENV_SECT_SIZE \
621 #define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \
622 - CFG_MEM_END_USAGE )
624 /* valid baudrates */
625 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
628 * Low Level Configuration Settings
629 * (address mappings, register initial values, etc.)
630 * You should know what you are doing if you make changes here.
633 #define CFG_FLASH_BASE CFG_FLASH0_BASE
634 #define CFG_FLASH_SIZE CFG_FLASH0_SIZE
635 #define CFG_SDRAM_BASE CFG_SDRAM0_BASE
636 #define CFG_SDRAM_SIZE CFG_SDRAM0_SIZE
638 /*-----------------------------------------------------------------------
639 * Hard Reset Configuration Words
641 #if defined(CFG_SBC_BOOT_LOW)
642 # define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
644 # define CFG_SBC_HRCW_BOOT_FLAGS (0)
645 #endif /* defined(CFG_SBC_BOOT_LOW) */
647 /* get the HRCW ISB field from CFG_IMMR */
648 #define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \
649 ((CFG_IMMR & 0x01000000) >> 7) | \
650 ((CFG_IMMR & 0x00100000) >> 4) )
652 #define CFG_HRCW_MASTER ( HRCW_BPS10 | \
654 CFG_SBC_HRCW_IMMR | \
659 (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) | \
660 CFG_SBC_HRCW_BOOT_FLAGS )
663 #define CFG_HRCW_SLAVE1 0
664 #define CFG_HRCW_SLAVE2 0
665 #define CFG_HRCW_SLAVE3 0
666 #define CFG_HRCW_SLAVE4 0
667 #define CFG_HRCW_SLAVE5 0
668 #define CFG_HRCW_SLAVE6 0
669 #define CFG_HRCW_SLAVE7 0
671 /*-----------------------------------------------------------------------
672 * Definitions for initial stack pointer and data area (in DPRAM)
674 #define CFG_INIT_RAM_ADDR CFG_IMMR
675 #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
676 #define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
677 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
678 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
680 /*-----------------------------------------------------------------------
681 * Start addresses for the final memory configuration
682 * (Set up by the startup code)
683 * Please note that CFG_SDRAM_BASE _must_ start at 0
684 * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
686 #define CFG_MONITOR_BASE CFG_FLASH0_BASE
688 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
692 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
693 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
696 * For booting Linux, the board info and command line data
697 * have to be in the first 8 MB of memory, since this is
698 * the maximum mapped by the Linux kernel during initialization.
700 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
702 /*-----------------------------------------------------------------------
703 * FLASH and environment organization
706 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
707 #undef CFG_FLASH_PROTECTION /* use hardware protection */
708 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
709 #define CFG_MAX_FLASH_SECT (64+4) /* max number of sectors on one chip */
711 #define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
712 #define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
715 # define CFG_ENV_IS_IN_FLASH 1
717 # ifdef CFG_ENV_IN_OWN_SECT
718 # define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
719 # define CFG_ENV_SECT_SIZE 0x10000
721 # define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
722 # define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
723 # define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
724 # endif /* CFG_ENV_IN_OWN_SECT */
727 # define CFG_ENV_IS_IN_NVRAM 1
728 # define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
729 # define CFG_ENV_SIZE 0x200
730 #endif /* CFG_RAMBOOT */
732 /*-----------------------------------------------------------------------
733 * Cache Configuration
735 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
737 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
738 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
741 /*-----------------------------------------------------------------------
742 * HIDx - Hardware Implementation-dependent Registers 2-11
743 *-----------------------------------------------------------------------
744 * HID0 also contains cache control - initially enable both caches and
745 * invalidate contents, then the final state leaves only the instruction
746 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
747 * but Soft reset does not.
749 * HID1 has only read-only information - nothing to set.
751 #define CFG_HID0_INIT (HID0_ICE |\
758 #define CFG_HID0_FINAL (HID0_ICE |\
764 /*-----------------------------------------------------------------------
765 * RMR - Reset Mode Register
766 *-----------------------------------------------------------------------
770 /*-----------------------------------------------------------------------
771 * BCR - Bus Configuration 4-25
772 *-----------------------------------------------------------------------
774 #define CFG_BCR (BCR_ETM)
776 /*-----------------------------------------------------------------------
777 * SIUMCR - SIU Module Configuration 4-31
778 *-----------------------------------------------------------------------
781 #define CFG_SIUMCR (SIUMCR_DPPC11 |\
787 /*-----------------------------------------------------------------------
788 * SYPCR - System Protection Control 11-9
789 * SYPCR can only be written once after reset!
790 *-----------------------------------------------------------------------
791 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
793 #if defined(CONFIG_WATCHDOG)
794 #define CFG_SYPCR (SYPCR_SWTC |\
802 #define CFG_SYPCR (SYPCR_SWTC |\
808 #endif /* CONFIG_WATCHDOG */
810 /*-----------------------------------------------------------------------
811 * TMCNTSC - Time Counter Status and Control 4-40
812 *-----------------------------------------------------------------------
813 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
814 * and enable Time Counter
816 #define CFG_TMCNTSC (TMCNTSC_SEC |\
821 /*-----------------------------------------------------------------------
822 * PISCR - Periodic Interrupt Status and Control 4-42
823 *-----------------------------------------------------------------------
824 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
827 #define CFG_PISCR (PISCR_PS |\
831 /*-----------------------------------------------------------------------
832 * SCCR - System Clock Control 9-8
833 *-----------------------------------------------------------------------
837 /*-----------------------------------------------------------------------
838 * RCCR - RISC Controller Configuration 13-7
839 *-----------------------------------------------------------------------
844 * Initialize Memory Controller:
846 * Bank Bus Machine PortSz Device
847 * ---- --- ------- ------ ------
848 * 0 60x GPCM 16 bit FLASH (primary flash - 2MB)
849 * 1 60x GPCM -- bit (Unused)
850 * 2 60x SDRAM 64 bit SDRAM (DIMM)
851 * 3 60x SDRAM 64 bit SDRAM (DIMM)
852 * 4 60x GPCM -- bit (Unused)
853 * 5 60x GPCM -- bit (Unused)
854 * 6 60x GPCM 16 bit FLASH (secondary flash - 2MB)
857 /*-----------------------------------------------------------------------
858 * BR0,BR1 - Base Register
859 * Ref: Section 10.3.1 on page 10-14
860 * OR0,OR1 - Option Register
861 * Ref: Section 10.3.2 on page 10-18
862 *-----------------------------------------------------------------------
865 /* Bank 0 - Primary FLASH
868 /* BR0 is configured as follows:
870 * - Base address of 0x40000000
872 * - Data errors checking is disabled
873 * - Read and write access
875 * - Access are handled by the memory controller according to MSEL
876 * - Not used for atomic operations
877 * - No data pipelining is done
880 #define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
885 /* OR0 is configured as follows:
888 * - *BCTL0 is asserted upon access to the current memory bank
889 * - *CW / *WE are negated a quarter of a clock earlier
890 * - *CS is output at the same time as the address lines
891 * - Uses a clock cycle length of 5
892 * - *PSDVAL is generated internally by the memory controller
893 * unless *GTA is asserted earlier externally.
894 * - Relaxed timing is generated by the GPCM for accesses
895 * initiated to this memory region.
896 * - One idle clock is inserted between a read access from the
897 * current bank and the next access.
899 #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
906 /*-----------------------------------------------------------------------
907 * BR2,BR3 - Base Register
908 * Ref: Section 10.3.1 on page 10-14
909 * OR2,OR3 - Option Register
910 * Ref: Section 10.3.2 on page 10-16
911 *-----------------------------------------------------------------------
914 /* Bank 2,3 - SDRAM DIMM
917 /* The BR2 is configured as follows:
919 * - Base address of 0x00000000
920 * - 64 bit port size (60x bus only)
921 * - Data errors checking is disabled
922 * - Read and write access
924 * - Access are handled by the memory controller according to MSEL
925 * - Not used for atomic operations
926 * - No data pipelining is done
929 #define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
934 #define CFG_BR3_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
939 /* With a 64 MB DIMM, the OR2 is configured as follows:
942 * - 4 internal banks per device
943 * - Row start address bit is A8 with PSDMR[PBI] = 0
944 * - 12 row address lines
945 * - Back-to-back page mode
946 * - Internal bank interleaving within save device enabled
948 #if (CFG_SDRAM0_SIZE == 64)
949 #define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
951 ORxS_ROWST_PBI0_A8 |\
954 #error "INVALID SDRAM CONFIGURATION"
957 /*-----------------------------------------------------------------------
958 * PSDMR - 60x Bus SDRAM Mode Register
959 * Ref: Section 10.3.3 on page 10-21
960 *-----------------------------------------------------------------------
963 /* Address that the DIMM SPD memory lives at.
965 #define SDRAM_SPD_ADDR 0x50
967 #if (CFG_SDRAM0_SIZE == 64)
968 /* With a 64 MB DIMM, the PSDMR is configured as follows:
970 * - Bank Based Interleaving,
972 * - Address Multiplexing where A5 is output on A14 pin
973 * (A6 on A15, and so on),
974 * - use address pins A14-A16 as bank select,
975 * - A9 is output on SDA10 during an ACTIVATE command,
976 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
977 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
979 * - earliest timing for READ/WRITE command after ACTIVATE command is
981 * - earliest timing for PRECHARGE after last data was read is 1 clock,
982 * - earliest timing for PRECHARGE after last data was written is 1 clock,
983 * - CAS Latency is 2.
985 #define CFG_PSDMR (PSDMR_RFEN |\
986 PSDMR_SDAM_A14_IS_A5 |\
987 PSDMR_BSMA_A14_A16 |\
988 PSDMR_SDA10_PBI0_A9 |\
996 #error "INVALID SDRAM CONFIGURATION"
1000 * Shoot for approximately 1MHz on the prescaler.
1002 #if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000))
1003 #define CFG_MPTPR MPTPR_PTP_DIV64
1004 #elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000))
1005 #define CFG_MPTPR MPTPR_PTP_DIV32
1007 #warning "Unconfigured bus clock freq: check CFG_MPTPR and CFG_PSRT are OK"
1008 #define CFG_MPTPR MPTPR_PTP_DIV32
1013 /*-----------------------------------------------------------------------
1014 * BR6 - Base Register
1015 * Ref: Section 10.3.1 on page 10-14
1016 * OR6 - Option Register
1017 * Ref: Section 10.3.2 on page 10-18
1018 *-----------------------------------------------------------------------
1021 /* Bank 6 - Secondary FLASH
1023 * The secondary FLASH is connected to *CS6
1025 #if (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE))
1027 /* BR6 is configured as follows:
1029 * - Base address of 0x60000000
1030 * - 16 bit port size
1031 * - Data errors checking is disabled
1032 * - Read and write access
1034 * - Access are handled by the memory controller according to MSEL
1035 * - Not used for atomic operations
1036 * - No data pipelining is done
1039 # define CFG_BR6_PRELIM ((CFG_FLASH1_BASE & BRx_BA_MSK) |\
1044 /* OR6 is configured as follows:
1047 * - *BCTL0 is asserted upon access to the current memory bank
1048 * - *CW / *WE are negated a quarter of a clock earlier
1049 * - *CS is output at the same time as the address lines
1050 * - Uses a clock cycle length of 5
1051 * - *PSDVAL is generated internally by the memory controller
1052 * unless *GTA is asserted earlier externally.
1053 * - Relaxed timing is generated by the GPCM for accesses
1054 * initiated to this memory region.
1055 * - One idle clock is inserted between a read access from the
1056 * current bank and the next access.
1058 # define CFG_OR6_PRELIM (MEG_TO_AM(CFG_FLASH1_SIZE) |\
1064 #endif /* (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) */
1067 * Internal Definitions
1071 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
1072 #define BOOTFLAG_WARM 0x02 /* Software reboot */
1074 #endif /* __CONFIG_H */