3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
33 * High Level Configuration Options
38 #define CONFIG_MPC850 1 /* This is a MPC850 CPU */
39 #define CONFIG_RPXLITE 1 /* RMU is the RPXlite clone */
42 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
43 #undef CONFIG_8xx_CONS_SMC2
44 #undef CONFIG_8xx_CONS_NONE
45 #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
47 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
49 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
52 #undef CONFIG_BOOTARGS
53 #define CONFIG_BOOTCOMMAND \
55 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
56 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
59 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
60 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
62 /* enable I2C and select the hardware/software driver */
63 #undef CONFIG_HARD_I2C /* I2C with hardware support */
64 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
66 #define CFG_I2C_SPEED 40000 /* 40 kHz is supposed to work */
67 #define CFG_I2C_SLAVE 0xFE
69 /* Software (bit-bang) I2C driver configuration */
70 #define PB_SCL 0x00000020 /* PB 26 */
71 #define PB_SDA 0x00000010 /* PB 27 */
73 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
74 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
75 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
76 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
77 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
78 else immr->im_cpm.cp_pbdat &= ~PB_SDA
79 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
80 else immr->im_cpm.cp_pbdat &= ~PB_SCL
81 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
83 /* M41T11 Serial Access Timekeeper(R) SRAM */
84 #define CONFIG_RTC_M41T11 1
85 #define CFG_I2C_RTC_ADDR 0x68
86 #define CFG_M41T11_BASE_YEAR 1900 /* play along with the linux driver */
88 #undef CONFIG_WATCHDOG /* watchdog disabled */
90 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
95 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
97 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
98 #include <cmd_confdefs.h>
100 #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
101 #define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n"
102 #define CONFIG_AUTOBOOT_DELAY_STR "system"
105 * Miscellaneous configurable options
107 #define CFG_LONGHELP /* undef to save memory */
108 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
109 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
110 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
112 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
114 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
115 #define CFG_MAXARGS 16 /* max number of command args */
116 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
118 #define CFG_MEMTEST_START 0x0040000 /* memtest works on */
119 #define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */
121 #define CFG_LOAD_ADDR 0x100000 /* default load address */
123 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
125 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
128 * Low Level Configuration Settings
129 * (address mappings, register initial values, etc.)
130 * You should know what you are doing if you make changes here.
132 /*-----------------------------------------------------------------------
133 * Internal Memory Mapped Register
135 #define CFG_IMMR 0xFA200000
137 /*-----------------------------------------------------------------------
138 * Definitions for initial stack pointer and data area (in DPRAM)
140 #define CFG_INIT_RAM_ADDR CFG_IMMR
141 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
142 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
143 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
144 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
146 /*-----------------------------------------------------------------------
147 * Start addresses for the final memory configuration
148 * (Set up by the startup code)
149 * Please note that CFG_SDRAM_BASE _must_ start at 0
151 #define CFG_SDRAM_BASE 0x00000000
152 #define CFG_FLASH_BASE (0-flash_info[0].size) /* Put flash at end */
153 #if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
154 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
156 #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
158 #define CFG_MONITOR_BASE TEXT_BASE
159 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
162 * For booting Linux, the board info and command line data
163 * have to be in the first 8 MB of memory, since this is
164 * the maximum mapped by the Linux kernel during initialization.
166 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
168 /*-----------------------------------------------------------------------
171 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
172 #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
174 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
175 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
177 #define CFG_ENV_IS_IN_FLASH 1
178 #define CFG_ENV_ADDR ((TEXT_BASE) + 0x40000)
179 #define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
181 /* Address and size of Redundant Environment Sector */
182 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SIZE)
183 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
185 /*-----------------------------------------------------------------------
188 #define CFG_RESET_ADDRESS ((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res)))
190 /*-----------------------------------------------------------------------
191 * Cache Configuration
193 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
194 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
195 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
198 /*-----------------------------------------------------------------------
199 * SYPCR - System Protection Control 11-9
200 * SYPCR can only be written once after reset!
201 *-----------------------------------------------------------------------
202 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
204 #if defined(CONFIG_WATCHDOG)
205 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
206 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
208 #define CFG_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
211 /*-----------------------------------------------------------------------
212 * SIUMCR - SIU Module Configuration 11-6
213 *-----------------------------------------------------------------------
214 * PCMCIA config., multi-function pin tri-state
216 #define CFG_SIUMCR (SIUMCR_MLRC10)
218 /*-----------------------------------------------------------------------
219 * TBSCR - Time Base Status and Control 11-26
220 *-----------------------------------------------------------------------
221 * Clear Reference Interrupt Status, Timebase freezing enabled
223 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
225 /*-----------------------------------------------------------------------
226 * RTCSC - Real-Time Clock Status and Control Register 11-27
227 *-----------------------------------------------------------------------
229 /*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
230 #define CFG_RTCSC (RTCSC_SEC | RTCSC_RTE)
232 /*-----------------------------------------------------------------------
233 * PISCR - Periodic Interrupt Status and Control 11-31
234 *-----------------------------------------------------------------------
235 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
237 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
239 /*-----------------------------------------------------------------------
240 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
241 *-----------------------------------------------------------------------
242 * Reset PLL lock status sticky bit, timer expired status bit and timer
243 * interrupt status bit
245 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
247 /* up to 50 MHz we use a 1:1 clock */
248 #define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
250 /*-----------------------------------------------------------------------
251 * SCCR - System Clock and reset Control Register 15-27
252 *-----------------------------------------------------------------------
253 * Set clock output, timebase and RTC source and divider,
254 * power management and some other internal clocks
256 #define SCCR_MASK SCCR_EBDF00
257 /* up to 50 MHz we use a 1:1 clock */
258 #define CFG_SCCR (SCCR_COM00 | SCCR_TBS)
260 /*-----------------------------------------------------------------------
262 *-----------------------------------------------------------------------
265 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
266 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
267 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
268 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
269 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
270 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
271 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
272 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
274 /*-----------------------------------------------------------------------
275 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
276 *-----------------------------------------------------------------------
279 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
281 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
282 #undef CONFIG_IDE_LED /* LED for ide not supported */
283 #undef CONFIG_IDE_RESET /* reset for ide not supported */
285 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
286 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
288 #define CFG_ATA_IDE0_OFFSET 0x0000
290 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
292 /* Offset for data I/O */
293 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
295 /* Offset for normal register accesses */
296 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
298 /* Offset for alternate registers */
299 #define CFG_ATA_ALT_OFFSET 0x0100
301 /*-----------------------------------------------------------------------
303 *-----------------------------------------------------------------------
306 /*#define CFG_DER 0x2002000F*/
310 * Init Memory Controller:
312 * BR0 and OR0 (FLASH)
315 #define FLASH_BASE_PRELIM 0xFC000000 /* FLASH base - up to 64 MB of flash */
316 #define CFG_PRELIM_OR_AM 0xFC000000 /* OR addr mask - map 64 MB */
318 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
319 #define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
321 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
322 #define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
325 * BR1 and OR1 (SDRAM)
328 #define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
329 #define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */
331 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
332 #define CFG_OR_TIMING_SDRAM 0x00000E00
334 #define CFG_OR1_PRELIM (0xF0000000 | CFG_OR_TIMING_SDRAM ) /* map 256 MB */
335 #define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
337 /* RPXLITE mem setting */
338 #define CFG_NVRAM_BASE 0xFA000000 /* NVRAM & SRAM base */
339 /* IMMR: 0xFA200000 IMMR base address - see above */
340 #define CFG_BCSR_BASE 0xFA400000 /* BCSR base address */
342 #define CFG_BR3_PRELIM (CFG_BCSR_BASE | BR_V) /* BCSR */
343 #define CFG_OR3_PRELIM 0xFFFF8910
344 #define CFG_BR4_PRELIM (CFG_NVRAM_BASE | BR_PS_8 | BR_V) /* NVRAM & SRAM */
345 #define CFG_OR4_PRELIM 0xFFFE0970
348 * Memory Periodic Timer Prescaler
351 /* periodic timer for refresh */
352 #define CFG_MAMR_PTA 20
355 * Refresh clock Prescalar
357 #define CFG_MPTPR MPTPR_PTP_DIV2
360 * MAMR settings for SDRAM
364 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
365 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
366 MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
369 * Internal Definitions
373 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
374 #define BOOTFLAG_WARM 0x02 /* Software reboot */
379 * Board Status and Control Registers
383 #define BCSR0 (CFG_BCSR_BASE + 0)
384 #define BCSR1 (CFG_BCSR_BASE + 1)
385 #define BCSR2 (CFG_BCSR_BASE + 2)
386 #define BCSR3 (CFG_BCSR_BASE + 3)
388 #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
389 #define BCSR0_ENNVRAM 0x02 /* CS4# Control */
390 #define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
391 #define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
392 #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
393 #define BCSR0_COLTEST 0x20
394 #define BCSR0_ETHLPBK 0x40
395 #define BCSR0_ETHEN 0x80
397 #define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
398 #define BCSR1_PCVCTL6 0x02
399 #define BCSR1_PCVCTL5 0x04
400 #define BCSR1_PCVCTL4 0x08
401 #define BCSR1_IPB5SEL 0x10
403 #define BCSR2_ENPA5HDR 0x08 /* USB Control */
404 #define BCSR2_ENUSBCLK 0x10
405 #define BCSR2_USBPWREN 0x20
406 #define BCSR2_USBSPD 0x40
407 #define BCSR2_USBSUSP 0x80
409 #define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
410 #define BCSR3_BWNVR 0x02 /* NVRAM Battery */
411 #define BCSR3_RDY_BSY 0x04 /* Flash Operation */
412 #define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
413 #define BCSR3_D27 0x10 /* Dip Switch settings */
414 #define BCSR3_D26 0x20
415 #define BCSR3_D25 0x40
416 #define BCSR3_D24 0x80
418 #endif /* __CONFIG_H */