2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
33 * High Level Configuration Options
38 #define CONFIG_MPC850 1 /* This is a MPC850 CPU */
39 #define CONFIG_RPXLITE 1 /* RMU is the RPXlite clone */
42 #define CONFIG_SYS_TEXT_BASE 0xfff00000
44 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
45 #undef CONFIG_8xx_CONS_SMC2
46 #undef CONFIG_8xx_CONS_NONE
47 #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
49 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
51 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
54 #undef CONFIG_BOOTARGS
55 #define CONFIG_BOOTCOMMAND \
57 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
58 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
61 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
62 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
64 /* enable I2C and select the hardware/software driver */
65 #undef CONFIG_HARD_I2C /* I2C with hardware support */
66 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
68 #define CONFIG_SYS_I2C_SPEED 40000 /* 40 kHz is supposed to work */
69 #define CONFIG_SYS_I2C_SLAVE 0xFE
71 /* Software (bit-bang) I2C driver configuration */
72 #define PB_SCL 0x00000020 /* PB 26 */
73 #define PB_SDA 0x00000010 /* PB 27 */
75 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
76 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
77 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
78 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
79 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
80 else immr->im_cpm.cp_pbdat &= ~PB_SDA
81 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
82 else immr->im_cpm.cp_pbdat &= ~PB_SCL
83 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
85 /* M41T11 Serial Access Timekeeper(R) SRAM */
86 #define CONFIG_RTC_M41T11 1
87 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
88 #define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with the linux driver */
90 #undef CONFIG_WATCHDOG /* watchdog disabled */
94 * Command line configuration.
96 #include <config_cmd_default.h>
98 #define CONFIG_CMD_DATE
99 #define CONFIG_CMD_DHCP
100 #define CONFIG_CMD_I2C
101 #define CONFIG_CMD_NFS
102 #define CONFIG_CMD_SNTP
108 #define CONFIG_BOOTP_SUBNETMASK
109 #define CONFIG_BOOTP_GATEWAY
110 #define CONFIG_BOOTP_HOSTNAME
111 #define CONFIG_BOOTP_BOOTPATH
112 #define CONFIG_BOOTP_BOOTFILESIZE
115 #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
116 #define CONFIG_AUTOBOOT_PROMPT \
117 "\nEnter password - autoboot in %d sec...\n", bootdelay
118 #define CONFIG_AUTOBOOT_DELAY_STR "system"
121 * Miscellaneous configurable options
123 #define CONFIG_SYS_LONGHELP /* undef to save memory */
124 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
125 #if defined(CONFIG_CMD_KGDB)
126 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
128 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
130 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
131 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
132 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
134 #define CONFIG_SYS_MEMTEST_START 0x0040000 /* memtest works on */
135 #define CONFIG_SYS_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */
137 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
139 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
141 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
144 * Low Level Configuration Settings
145 * (address mappings, register initial values, etc.)
146 * You should know what you are doing if you make changes here.
148 /*-----------------------------------------------------------------------
149 * Internal Memory Mapped Register
151 #define CONFIG_SYS_IMMR 0xFA200000
153 /*-----------------------------------------------------------------------
154 * Definitions for initial stack pointer and data area (in DPRAM)
156 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
157 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
158 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
159 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
161 /*-----------------------------------------------------------------------
162 * Start addresses for the final memory configuration
163 * (Set up by the startup code)
164 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
166 #define CONFIG_SYS_SDRAM_BASE 0x00000000
167 #define CONFIG_SYS_FLASH_BASE (0-flash_info[0].size) /* Put flash at end */
168 #if defined(DEBUG) || defined(CONFIG_CMD_IDE)
169 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
171 #define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
173 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
174 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
177 * For booting Linux, the board info and command line data
178 * have to be in the first 8 MB of memory, since this is
179 * the maximum mapped by the Linux kernel during initialization.
181 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
183 /*-----------------------------------------------------------------------
186 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
187 #define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
189 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
190 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
192 #define CONFIG_ENV_IS_IN_FLASH 1
193 #define CONFIG_ENV_ADDR ((CONFIG_SYS_TEXT_BASE) + 0x40000)
194 #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
195 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Used size for environment */
197 /* Address and size of Redundant Environment Sector */
198 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
199 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
201 /*-----------------------------------------------------------------------
204 #define CONFIG_SYS_RESET_ADDRESS ((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res)))
206 /*-----------------------------------------------------------------------
207 * Cache Configuration
209 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
210 #if defined(CONFIG_CMD_KGDB)
211 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
214 /*-----------------------------------------------------------------------
215 * SYPCR - System Protection Control 11-9
216 * SYPCR can only be written once after reset!
217 *-----------------------------------------------------------------------
218 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
220 #if defined(CONFIG_WATCHDOG)
221 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
222 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
224 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
227 /*-----------------------------------------------------------------------
228 * SIUMCR - SIU Module Configuration 11-6
229 *-----------------------------------------------------------------------
230 * PCMCIA config., multi-function pin tri-state
232 #define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10)
234 /*-----------------------------------------------------------------------
235 * TBSCR - Time Base Status and Control 11-26
236 *-----------------------------------------------------------------------
237 * Clear Reference Interrupt Status, Timebase freezing enabled
239 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
241 /*-----------------------------------------------------------------------
242 * RTCSC - Real-Time Clock Status and Control Register 11-27
243 *-----------------------------------------------------------------------
245 /*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
246 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_RTE)
248 /*-----------------------------------------------------------------------
249 * PISCR - Periodic Interrupt Status and Control 11-31
250 *-----------------------------------------------------------------------
251 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
253 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
255 /*-----------------------------------------------------------------------
256 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
257 *-----------------------------------------------------------------------
258 * Reset PLL lock status sticky bit, timer expired status bit and timer
259 * interrupt status bit
261 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
263 /* up to 50 MHz we use a 1:1 clock */
264 #define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
266 /*-----------------------------------------------------------------------
267 * SCCR - System Clock and reset Control Register 15-27
268 *-----------------------------------------------------------------------
269 * Set clock output, timebase and RTC source and divider,
270 * power management and some other internal clocks
272 #define SCCR_MASK SCCR_EBDF00
273 /* up to 50 MHz we use a 1:1 clock */
274 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS)
276 /*-----------------------------------------------------------------------
278 *-----------------------------------------------------------------------
281 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
282 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
283 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
284 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
285 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
286 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
287 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
288 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
290 /*-----------------------------------------------------------------------
291 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
292 *-----------------------------------------------------------------------
295 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
297 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
298 #undef CONFIG_IDE_LED /* LED for ide not supported */
299 #undef CONFIG_IDE_RESET /* reset for ide not supported */
301 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
302 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
304 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
306 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
308 /* Offset for data I/O */
309 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
311 /* Offset for normal register accesses */
312 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
314 /* Offset for alternate registers */
315 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
317 /*-----------------------------------------------------------------------
319 *-----------------------------------------------------------------------
322 /*#define CONFIG_SYS_DER 0x2002000F*/
323 #define CONFIG_SYS_DER 0
326 * Init Memory Controller:
328 * BR0 and OR0 (FLASH)
331 #define FLASH_BASE_PRELIM 0xFC000000 /* FLASH base - up to 64 MB of flash */
332 #define CONFIG_SYS_PRELIM_OR_AM 0xFC000000 /* OR addr mask - map 64 MB */
334 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
335 #define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
337 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
338 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
341 * BR1 and OR1 (SDRAM)
344 #define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
345 #define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */
347 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
348 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00
350 #define CONFIG_SYS_OR1_PRELIM (0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM ) /* map 256 MB */
351 #define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
353 /* RPXLITE mem setting */
354 #define CONFIG_SYS_NVRAM_BASE 0xFA000000 /* NVRAM & SRAM base */
355 /* IMMR: 0xFA200000 IMMR base address - see above */
356 #define CONFIG_SYS_BCSR_BASE 0xFA400000 /* BCSR base address */
358 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_BASE | BR_V) /* BCSR */
359 #define CONFIG_SYS_OR3_PRELIM 0xFFFF8910
360 #define CONFIG_SYS_BR4_PRELIM (CONFIG_SYS_NVRAM_BASE | BR_PS_8 | BR_V) /* NVRAM & SRAM */
361 #define CONFIG_SYS_OR4_PRELIM 0xFFFE0970
364 * Memory Periodic Timer Prescaler
367 /* periodic timer for refresh */
368 #define CONFIG_SYS_MAMR_PTA 20
371 * Refresh clock Prescalar
373 #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV2
376 * MAMR settings for SDRAM
380 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
381 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
382 MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
387 * Board Status and Control Registers
391 #define BCSR0 (CONFIG_SYS_BCSR_BASE + 0)
392 #define BCSR1 (CONFIG_SYS_BCSR_BASE + 1)
393 #define BCSR2 (CONFIG_SYS_BCSR_BASE + 2)
394 #define BCSR3 (CONFIG_SYS_BCSR_BASE + 3)
396 #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
397 #define BCSR0_ENNVRAM 0x02 /* CS4# Control */
398 #define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
399 #define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
400 #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
401 #define BCSR0_COLTEST 0x20
402 #define BCSR0_ETHLPBK 0x40
403 #define BCSR0_ETHEN 0x80
405 #define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
406 #define BCSR1_PCVCTL6 0x02
407 #define BCSR1_PCVCTL5 0x04
408 #define BCSR1_PCVCTL4 0x08
409 #define BCSR1_IPB5SEL 0x10
411 #define BCSR2_ENPA5HDR 0x08 /* USB Control */
412 #define BCSR2_ENUSBCLK 0x10
413 #define BCSR2_USBPWREN 0x20
414 #define BCSR2_USBSPD 0x40
415 #define BCSR2_USBSUSP 0x80
417 #define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
418 #define BCSR3_BWNVR 0x02 /* NVRAM Battery */
419 #define BCSR3_RDY_BSY 0x04 /* Flash Operation */
420 #define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
421 #define BCSR3_D27 0x10 /* Dip Switch settings */
422 #define BCSR3_D26 0x20
423 #define BCSR3_D25 0x40
424 #define BCSR3_D24 0x80
426 #endif /* __CONFIG_H */