1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2021 Rockchip Electronics Co., Ltd
4 * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
7 #ifndef __CONFIG_RK3588_COMMON_H
8 #define __CONFIG_RK3588_COMMON_H
10 #include "rockchip-common.h"
12 #define CFG_IRAM_BASE 0xff000000
14 #define CFG_SYS_SDRAM_BASE 0
15 #define SDRAM_MAX_SIZE 0xf0000000
17 #define ENV_MEM_LAYOUT_SETTINGS \
18 "scriptaddr=0x00c00000\0" \
19 "pxefile_addr_r=0x00e00000\0" \
20 "fdt_addr_r=0x0a100000\0" \
21 "kernel_addr_r=0x02080000\0" \
22 "ramdisk_addr_r=0x0a200000\0"
24 #include <config_distro_bootcmd.h>
25 #define CFG_EXTRA_ENV_SETTINGS \
26 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
27 "partitions=" PARTS_DEFAULT \
28 ENV_MEM_LAYOUT_SETTINGS \
29 ROCKCHIP_DEVICE_SETTINGS \
32 #endif /* __CONFIG_RK3588_COMMON_H */