1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2021 Rockchip Electronics Co., Ltd
6 #ifndef __CONFIG_RK3568_COMMON_H
7 #define __CONFIG_RK3568_COMMON_H
9 #include "rockchip-common.h"
11 #define CONFIG_SYS_CBSIZE 1024
13 #define COUNTER_FREQUENCY 24000000
15 #define CONFIG_IRAM_BASE 0xfdcc0000
17 #define CONFIG_SYS_INIT_SP_ADDR 0x00c00000
19 #define CONFIG_SPL_STACK 0x00400000
20 #define CONFIG_SPL_MAX_SIZE 0x20000
21 #define CONFIG_SPL_BSS_START_ADDR 0x4000000
22 #define CONFIG_SPL_BSS_MAX_SIZE 0x4000
24 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
26 #define CONFIG_SYS_SDRAM_BASE 0
27 #define SDRAM_MAX_SIZE 0xf0000000
29 #ifndef CONFIG_SPL_BUILD
30 #define ENV_MEM_LAYOUT_SETTINGS \
31 "scriptaddr=0x00c00000\0" \
32 "pxefile_addr_r=0x00e00000\0" \
33 "fdt_addr_r=0x0a100000\0" \
34 "kernel_addr_r=0x02080000\0" \
35 "ramdisk_addr_r=0x0a200000\0"
37 #include <config_distro_bootcmd.h>
38 #define CONFIG_EXTRA_ENV_SETTINGS \
39 ENV_MEM_LAYOUT_SETTINGS \
40 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
41 "partitions=" PARTS_DEFAULT \
42 ROCKCHIP_DEVICE_SETTINGS \